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594 Commits

Author SHA1 Message Date
matt f8b9dbe468 Add some MPC745x L3CR cache definitions. 2002-04-03 00:12:41 +00:00
matt 830666e31e Clean the icache for pages when they are entered as executable and before 
they were either not mapped at all or mapped as non-executable.  Round
memory regions in pmap_bootstrap.
 2002-04-03 00:12:07 +00:00
matt 7e121bd39d Properly print out 745x cache information. 2002-04-03 00:09:52 +00:00
eeh 67c9b24c04 Follow the post-UBC semantics of resetting ref/mod collection inside of 
pmap_clear_{reference,modify}().
 2002-03-28 18:07:31 +00:00
kleink 1b6af7fb37 Add separate 601 versions of DSI/ISI trap entries, considering the 
different battable entry format and the combined BAT implementation.
 2002-03-27 15:40:46 +00:00
kleink 032762e1e9 On the 601, construct the CPU counter value from the RTC[UL] registers. 2002-03-26 21:50:39 +00:00
matt 12810ed37d Use size_t in prototype (so this will be LP64 clean for PPC64 someday). 
Calculate len separately for icache & dcache in case each has different
cacheline widths.  Make the code for both loops the same except for the
dcbst/icbi.  Deal with sizes >=2GB properly (like that'll happen but ...)
 2002-03-26 21:20:24 +00:00
kleink 7e9d845469 * Add MPC601 versions of BAT_VA_MATCH_P() and BAT_VALID_P(). 
* Make the extern declaration of the battable array incomplete;
  a given port might want to use a differently-sized definition to
  support the 601 BAT implementation, where blocks map up to 8M only.
 2002-03-25 21:35:45 +00:00
briggs a2e0bd5a5d Use p->p_psstr instead of PS_STRINGS. 
Tested on boot to multi-user on sandpoint.
 2002-03-18 04:50:32 +00:00
eeh 0754ce0386 Use properties instead of board_info. 2002-03-15 21:12:07 +00:00
eeh 75343f2177 Use new non-PCI mainbus. 2002-03-15 21:10:46 +00:00
eeh 5468c6fb37 Fixup distinguishing between user and kernel addresses for IBM 4xx CPUs. 2002-03-15 21:01:28 +00:00
eeh de5252061e Use properties to pass around board-specific information rather than a 
structure.
 2002-03-15 20:59:23 +00:00
eeh 7c79cb049f Some files have been moved into powerpc/ibm4xx. 2002-03-14 17:27:59 +00:00
eeh a3833eb1c6 Add this file. 2002-03-13 23:59:58 +00:00
eeh d26d3b351c This should be pretty standard. 2002-03-13 23:12:11 +00:00
eeh 2277f9518e Delete this file. It's only relevent to 405gp. 2002-03-13 23:09:52 +00:00
eeh 2b55b12b59 405gp-specific DCRs. 2002-03-13 23:09:11 +00:00
eeh 266bd056b2 Adapt to the new, separate mainbus. 2002-03-13 19:13:10 +00:00
eeh 8e235a382a Add a vector for machine check traps. 2002-03-13 19:11:53 +00:00
eeh d94ffa460b Generic mainbus driver. 2002-03-13 01:04:16 +00:00
eeh ba8ac60043 pmap improvements: 
Remove the cache flush routines that have been moved to cpu.c

Make sure we clear out the unused PA bits in the TTE which causes breakage
on some MMU models.
 2002-03-13 00:47:58 +00:00
eeh 9129e6fe1d Generalized IBM UIC driver. 2002-03-13 00:40:50 +00:00
eeh 4b971968ac Add cache_info to cpu_info which provides details about D$ and I$ 
sizes and line sizes.  This is needed for cache flusing, clearing
memory, and several other operations.  This information is accessible
from userland through a new CPU_CACHEINFO sysctl.
 2002-03-13 00:38:13 +00:00
chs bd2a5f591d switch all mpc6xx powerpc ports to NEWPMAP by default. 
the old pmap is still available with the OLDPMAP option.
 2002-03-09 23:35:56 +00:00
thorpej a180cee23b Pool deals fairly well with physical memory shortage, but it doesn't 
deal with shortages of the VM maps where the backing pages are mapped
(usually kmem_map).  Try to deal with this:

* Group all information about the backend allocator for a pool in a
  separate structure.  The pool references this structure, rather than
  the individual fields.
* Change the pool_init() API accordingly, and adjust all callers.
* Link all pools using the same backend allocator on a list.
* The backend allocator is responsible for waiting for physical memory
  to become available, but will still fail if it cannot callocate KVA
  space for the pages.  If this happens, carefully drain all pools using
  the same backend allocator, so that some KVA space can be freed.
* Change pool_reclaim() to indicate if it actually succeeded in freeing
  some pages, and use that information to make draining easier and more
  efficient.
* Get rid of PR_URGENT.  There was only one use of it, and it could be
  dealt with by the caller.

From art@openbsd.org.
 2002-03-08 20:48:27 +00:00
simonb abf4139889 Include libkern.h for strcmp() prototype. 2002-03-08 01:36:34 +00:00
tsutsui 3c8b0446fe Change type of dumpmag to u_int32_t since it is actually 
a 32bit unsigned magic number.
As per discussion on tech-kern, and fixes port-sparc64/11949.
 2002-03-06 13:10:18 +00:00
nathanw 3be9fbe42e Move #include <dev/sysmon/sysmonvar.h> inside #ifdef _KERNEL. 2002-03-06 06:37:17 +00:00
kleink 8a79f029ad VRSAVE is SPR 256, not 238. 2002-03-04 13:37:42 +00:00
dbj b5fde890d0 add cnpollc() calls around cngetc for TRAP_PANICWAIT 2002-03-04 04:07:35 +00:00
kleink 995081f947 Make this link again in the absence of envsys/sysmon. 2002-03-04 00:55:04 +00:00
nathanw b50fb54af2 Calculate and print the speed of G3 and G4 processors. 
Add code to read the on-chip temperature sensor on the G3 and hook it in
to the envsys/sysmon subsystem. "envstat" now prints the CPU temperature.
 2002-03-03 07:31:33 +00:00
nathanw 1eeb28024d Add sysmon data structures to struct cpu_info. 2002-03-03 07:09:09 +00:00
matt d26c78e764 All Moto PPC revisions should be printed as maj.min (0x0200 -> 2.0). 2002-03-03 07:09:01 +00:00
matt e0ba5cf38d Add initial MPC7455 support. 2002-03-03 06:56:09 +00:00
matt 997374a8dd Add MPC7455 2002-03-03 06:47:25 +00:00
nathanw 5d5aeaa547 Add bit definitions for the MMCR's, and event numbers for the events 
that are common to the G3 and G4.
 2002-03-03 06:38:31 +00:00
nathanw 7a92615001 Correct the SPR numbers of PMC3 and PMC4. 
SIA wasn't retconned, but the SPR number was wrong. Re-add it, and add
USIA.
 2002-03-03 05:32:37 +00:00
nathanw c2b8ec655a Delete the retconned SIAR SPR. 2002-03-03 05:17:48 +00:00
nathanw ee2cbbfe4a Add MPC7xx/7xxx performance monitor control registers (MMCR0-2, UMMCR0-2). 2002-03-03 05:15:44 +00:00
nathanw 28b2a20fb9 Add bit definitions for the MPC750 thermal management registers. 2002-03-03 04:31:53 +00:00
kleink 4a513728e8 Add end-of-comment missing in previous. 2002-03-02 21:36:27 +00:00
kleink a34187bca3 Also reset segment register 0 on kernel entry: there may not always be 
a fixed BAT entry covering segment 0, or not completely covering it,
and we do restore it on return to user level already.
 2002-03-02 15:19:56 +00:00
kleink dc0a08feaa Note that Guarded bit is not implemented on the 601. 2002-03-02 15:07:35 +00:00
matt 4b948be2fc Disable BTIC on rev 2.0 or earlier MPC7450s as Motorola Errata #31 for the 
MPC7450.
 2002-03-02 02:18:38 +00:00
simonb 4324f37586 Use "#define<tab>". 2002-02-28 03:17:23 +00:00
kleink 39a685458d Fix pastos & typoe. 2002-02-27 04:13:10 +00:00
matt 178af24f65 Add a comment to where we increment intr_depth to show that intstk+INTSTK 
== intr_depth. (gag)
 2002-02-27 03:27:14 +00:00
christos e8116a8f5b - Use DEV_ constants, instead of documenting the numbers! 
- Delete cdev_decl(mm); where appropriate, and other hand-crufting [hi powerpc!]
 2002-02-27 01:20:51 +00:00