TLBUpdate() routine is used for dual purposes. In TLBmod case, just ok
to call 'tlbwi' (as designed). Result in saving of extraneous execution
path. MIPS1 only this moment.
(correct name, vax?) replacing mips1_TLBFlushAddr and mips1_TLBUpdate,
respectively. New codes always use current ASID holded in EntryHi
register. In most occations, the register already contains a necessary
value before (re-)written, ugh. 'sva | asid' ops for their arguments are
now verbose, to be removed when MIPS3 side changes are done.
'pm_asid' member of 'pmap' structure is assigned a new value after
uvmspace_alloc() provides afresh pmap.
- ASID generation number 0 is not a reserved value anymore.
processor is one of processors with no 'referenced bit' nor 'modified bit'
processor machinary. Those functions are implemented combining two
hardware bits, 'dirty bit' and 'valid bit', with TLBmod exception handler.
per process user spaces, replacing mips1_TBLFlush(). This reserves
kernel space TLB entries when TLBPID generation number about to wrap.
- Correct comments a bit, nuke unused routines.
initialization code.
- Abandon mips_init_proc0() and do the 4 lines straightly in MD mach_init().
- Restore a block of code accidentally lost in prevous commit.
- Change the term 'tlbpid' to a MIPS3 nomenclature 'asid'.
- Hide PTE size exposures by symbolic names in locore.S
the child inherits the stack pointer from the parent (traditional
behavior). Like the signal stack, the stack area is secified as
a low address and a size; machine-dependent code accounts for stack
direction.
This is required for clone(2).
_splraise, _spllower, _splset, _splget, _setsoftintr, _clrsoftintr, _splnone.
They manipulate MIPS processor's 8 interrupt sources and are used
as building blocks for NetBSD spl(9) kernel interface. Note that
MIPS processor doesn't enforce inclusive 'interrupt levels' found
in other processors, then the hierarchal nature of IPL must be
implemented by composing MIPS processor interrupt masks appropriately.
With the simplest target port in which small number of devices are
independently assigned with 6 external interrupt signal lines,
spl(9) kernel interface will be implemented with #define's of
processor interrupt controls mentioned above. In more general
cases, in which target computers have many devices and 'system
registers' indicating pending interrupt sources at any moment,
spl(9) will be implemented with more complex machinary manipulating
processor interrupts and system registers in target port dependent
ways.
- Nuke unused code and reorder locore definitions. XXX Following
routines will be replaced with C language version; setrunqueue,
remrunqueue, switchfpregs, savefpregs, MachFPInterrupt.
- ALIAS() is not needed, use XLEAF() or XNESTED() instead
- use AENT() instead of .aent
- _END_LABEL() is not needed (and was wrong)
- define ALEAF(), NLEAF(), NON_LEAF(), NNON_LEAF() by
XLEAF(), LEAF_NONPROFILE(), NESTED(), NESTED_NONPROFILE()
* Map the message buffer with access_type = VM_PROT_READ|VM_PROT_WRITE `just
because'.
* Map the file system buffers with access_type = VM_PROT_READ|VM_PROT_WRITE to
avoid possible problems with pagemove().
* Do not use VM_PROT_EXEC with either of the above.
* Map pages for /dev/mem with access_type = prot. Also, DO NOT use
pmap_kenter() for this, as we DO NOT want to lose modification information.
* Map pages in dumpsys() with VM_PROT_READ.
* Map pages in m68k mappedcopyin()/mappedcopyout() and writeback() with
access_type = prot.
* For now, bus_dma*(), pmap_map(), vmapbuf(), and similar functions still use
access_type = 0. This should probably be revisited.
allocated from a pool, and the MIPS and Alpha use KSEG to map pool
pages. So, mb_map wasn't actually being used. Saves around 4MB of
kernel virtual address space in a typical configuration.
Garbage-collect the related VM_MBUF_SIZE constant.
nisimura