Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
36c4252a17
NetBSD/sys/arch/mips/include/locore.h

253 lines
7.2 KiB
C
Raw Normal View History

IDT32364's Config register uses a different base for IC/DC (instruction and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364 uses 2^(9+IC) and 2^(9+DC). abstract around the problem by making the base a parameter to the MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init to mips3_vector_init and to mips3_ConfigCache (where it is used). XXX: someone with an MIPS3_4100 should switch to this and get rid of the ugly ifdefs in cpuregs.h
2000-09-16 04:04:57 +04:00
/* $NetBSD: locore.h,v 1.42 2000/09/16 00:04:57 chuck Exp $ */
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
* Junior University. All Rights Reserved.
*
* Permission to use, copy, modify, and distribute this
* software and its documentation for any purpose and without
* fee is hereby granted, provided that the above copyright
* notice appear in all copies. Stanford University
* makes no representations about the suitability of this
* software for any purpose. It is provided "as is" without
* express or implied warranty.
*/
/*
* Jump table for MIPS cpu locore functions that are implemented
* differently on different generations, or instruction-level
* archtecture (ISA) level, the Mips family.
* The following functions must be provided for each mips ISA level:
*
Nuke register and remove trailling white space.
1999-04-24 12:01:01 +04:00
*
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
* MachFlushCache
* MachFlushDCache
* MachFlushICache
DECstation MIPS3 support: wbflush() is cpu-dependent, need declaration from machine/locore.h. From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through proc_trampoline() [also cpu-dependent].
1997-06-15 21:33:53 +04:00
* wbflush
* proc_trampoline()
More merged mips1/mips3 support: Remove cpu-specific routines from locore.S and add them to locore_r2000.S and locore_r4000.S. Add entries in locore jump vector table for switch_exit() and the cpu_switch() context resume. Add offsets into the jump vector to genassym.cf for use in locore.S.
1997-06-19 10:31:14 +04:00
* cpu_switch_resume()
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
*
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD, so remove references them, and do a little other cleanup.
2000-05-23 08:21:39 +04:00
* We currently provide support for MIPS I and MIPS III.
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
*/
#ifndef _MIPS_LOCORE_H
#define _MIPS_LOCORE_H
Protect defopt against -D_LKM
1999-01-15 13:07:12 +03:00
#ifndef _LKM
Include opt_cputype.h.
2000-05-21 07:23:15 +04:00
#include "opt_cputype.h"
* Create mips_reg_t data type to allow register size to be decoupled from long or int or long long. Define macros in asm.h to facilitate choosing these on a port by port basis. * Create <machine/pubassym.h> mechanism to allow jmp_buf structure size to be calculated at system build time. * Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae for the architecture. For 64-bit oriented systems set the Status Register to allow 64-bit instructions. * Remove UADDR related macros because kernel U structure is now mapped normally. * Separate cpu.h into cpu.h and cpuarch.h to keep things neat. * Add support for QED 52xx processors
1999-01-14 21:45:45 +03:00
#include "opt_mips_cache.h"
Protect defopt against -D_LKM
1999-01-15 13:07:12 +03:00
#endif
* Create mips_reg_t data type to allow register size to be decoupled from long or int or long long. Define macros in asm.h to facilitate choosing these on a port by port basis. * Create <machine/pubassym.h> mechanism to allow jmp_buf structure size to be calculated at system build time. * Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae for the architecture. For 64-bit oriented systems set the Status Register to allow 64-bit instructions. * Remove UADDR related macros because kernel U structure is now mapped normally. * Separate cpu.h into cpu.h and cpuarch.h to keep things neat. * Add support for QED 52xx processors
1999-01-14 21:45:45 +03:00
un-__P, clean up spacing a little bit, put fwd struct decl(s) near top rather than embedded. no functional changes.
2000-06-29 10:00:43 +04:00
struct tlb;
* Move the declarations of mips locore functions from the pmax tree to the mips tree. * Add declarations of functions used by vm_machdep.c. * Add declarations of functions printed by name in stack tracebacks. * Add declarations of functions used by the model-independnet mips machdep.c code.
1996-05-21 03:38:26 +04:00
/*
* Create mips_reg_t data type to allow register size to be decoupled from long or int or long long. Define macros in asm.h to facilitate choosing these on a port by port basis. * Create <machine/pubassym.h> mechanism to allow jmp_buf structure size to be calculated at system build time. * Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae for the architecture. For 64-bit oriented systems set the Status Register to allow 64-bit instructions. * Remove UADDR related macros because kernel U structure is now mapped normally. * Separate cpu.h into cpu.h and cpuarch.h to keep things neat. * Add support for QED 52xx processors
1999-01-14 21:45:45 +03:00
* locore service routine for exception vectors. Used outside locore
* Move the declarations of mips locore functions from the pmax tree to the mips tree. * Add declarations of functions used by vm_machdep.c. * Add declarations of functions printed by name in stack tracebacks. * Add declarations of functions used by the model-independnet mips machdep.c code.
1996-05-21 03:38:26 +04:00
* only to print them by name in stack tracebacks
*/
un-__P, clean up spacing a little bit, put fwd struct decl(s) near top rather than embedded. no functional changes.
2000-06-29 10:00:43 +04:00
u_int32_t mips_read_causereg(void);
u_int32_t mips_read_statusreg(void);
void mips1_ConfigCache(void);
void mips1_FlushCache(void);
void mips1_FlushDCache(vaddr_t addr, vsize_t len);
void mips1_FlushICache(vaddr_t addr, vsize_t len);
void mips1_SetPID(int pid);
void mips1_TBIA(int);
void mips1_TBIAP(int);
void mips1_TBIS(vaddr_t);
int mips1_TLBUpdate(u_int, u_int);
void mips1_wbflush(void);
void mips1_proc_trampoline(void);
void mips1_cpu_switch_resume(void);
IDT32364's Config register uses a different base for IC/DC (instruction and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364 uses 2^(9+IC) and 2^(9+DC). abstract around the problem by making the base a parameter to the MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init to mips3_vector_init and to mips3_ConfigCache (where it is used). XXX: someone with an MIPS3_4100 should switch to this and get rid of the ugly ifdefs in cpuregs.h
2000-09-16 04:04:57 +04:00
void mips3_ConfigCache(int);
un-__P, clean up spacing a little bit, put fwd struct decl(s) near top rather than embedded. no functional changes.
2000-06-29 10:00:43 +04:00
void mips3_FlushCache(void);
void mips3_FlushDCache(vaddr_t addr, vaddr_t len);
void mips3_FlushICache(vaddr_t addr, vaddr_t len);
void mips3_HitFlushDCache(vaddr_t, int);
void mips3_SetPID(int pid);
void mips3_TBIA(int);
void mips3_TBIAP(int);
void mips3_TBIS(vaddr_t);
int mips3_TLBUpdate(u_int, u_int);
void mips3_TLBRead(int, struct tlb *);
void mips3_SetWIRED(int);
void mips3_wbflush(void);
void mips3_proc_trampoline(void);
void mips3_cpu_switch_resume(void);
void mips3_FlushCache_2way(void);
void mips3_FlushDCache_2way(vaddr_t addr, vaddr_t len);
void mips3_HitFlushDCache_2way(vaddr_t, int);
void mips3_FlushICache_2way(vaddr_t addr, vaddr_t len);
u_int32_t mips3_read_config(void);
u_int32_t mips3_cycle_count(void);
u_int32_t mips3_write_count(u_int32_t);
u_int32_t mips3_read_compare(void);
void mips3_write_config(u_int32_t);
void mips3_write_compare(u_int32_t);
void mips3_clearBEV(void);
Garbage-collect redundant declarations: mips/include/locore.h: Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here. mips/include/cpu.h: remove cpu_prid definition. pmax/pmax/machdep.c: remove local protoypes of HitFlushDCache() functions. mips/mips/vm_machdep.c, mips/mips/vm_machdep.c:: remove local protoypes of HitFlushDCache() functions.
1997-06-16 13:50:26 +04:00
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
/*
* A vector with an entry for each mips-ISA-level dependent
* locore function, and macros which jump through it.
* XXX the macro names are chosen to be compatible with the old
* Sprite coding-convention names used in 4.4bsd/pmax.
*/
typedef struct {
un-__P, clean up spacing a little bit, put fwd struct decl(s) near top rather than embedded. no functional changes.
2000-06-29 10:00:43 +04:00
void (*flushCache)(void);
void (*flushDCache)(vaddr_t addr, vsize_t len);
void (*flushICache)(vaddr_t addr, vsize_t len);
void (*setTLBpid)(int pid);
void (*TBIAP)(int);
void (*TBIS)(vaddr_t);
int (*tlbUpdate)(u_int highreg, u_int lowreg);
void (*wbflush)(void);
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
} mips_locore_jumpvec_t;
Commit change missed during Decsystem 5100 chagnes: prototype declearation for method to override wbflush() callback vector with model-specific code. Used on DEC r2000a machines with writebuffers which indicate writebuffer drain via cp0 usability bit.
1998-04-23 14:31:02 +04:00
/* Override writebuffer-drain method. */
un-__P, clean up spacing a little bit, put fwd struct decl(s) near top rather than embedded. no functional changes.
2000-06-29 10:00:43 +04:00
void mips_set_wbflush(void (*)(void));
Commit change missed during Decsystem 5100 chagnes: prototype declearation for method to override wbflush() callback vector with model-specific code. Used on DEC r2000a machines with writebuffers which indicate writebuffer drain via cp0 usability bit.
1998-04-23 14:31:02 +04:00
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
Prototype stacktrace() and logstacktrace().
2000-01-09 13:05:55 +03:00
/* stacktrace() -- print a stack backtrace to the console */
un-__P, clean up spacing a little bit, put fwd struct decl(s) near top rather than embedded. no functional changes.
2000-06-29 10:00:43 +04:00
void stacktrace(void);
Prototype stacktrace() and logstacktrace().
2000-01-09 13:05:55 +03:00
/* logstacktrace() -- log a stack traceback to msgbuf */
un-__P, clean up spacing a little bit, put fwd struct decl(s) near top rather than embedded. no functional changes.
2000-06-29 10:00:43 +04:00
void logstacktrace(void);
Prototype stacktrace() and logstacktrace().
2000-01-09 13:05:55 +03:00
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
/*
* The "active" locore-fuction vector, and
*/
extern mips_locore_jumpvec_t mips_locore_jumpvec;
extern mips_locore_jumpvec_t r2000_locore_vec;
extern mips_locore_jumpvec_t r4000_locore_vec;
Have mips_locoresw[] of 3 entry pointer array for different implementation of locore routines between MIPS1 and MIPS3. It's independent from mips_locore_jumpvec_t which is for cache/TLB manipulating routines peculiar to processor designs. mips_locore_jumpvec_t will be replaced with "processor closures" encapsulating implementation parameters (cpuinfo) and pointers to conventaion routines (cpuops), eventually.
2000-05-10 05:34:13 +04:00
extern long *mips_locoresw[];
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
Final changes for configuring MIPS1 and MIPS3 in a single kernel. * cpuregs.h: rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx. Add compile-time MIPS3-only, compile-time MIPS1-only, and runtime (both) definitions for number of TLB ASIDs (tlb pids) and shift count to extract a TLB pid. * locore.h: Delete unused vector slot for indexed TLB writes. mips1 and mips3 TLBs are different enough that we have to break them out at the caller anyway. * Add compile-time MIPS3-only andcompile-time MIPS1-only macros to call locore functions directly by name. Use the existing method table only if * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c: Use MIPS3_ or MIPS1_ specific names for TLB pids in mips3 and mips1 specific code paths (e.g., creating the kernel stack for process 0). Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 07:17:37 +04:00
#if defined(MIPS3) && !defined (MIPS1)
Rename RM5200 cache ops to mips3_*_2way in anticipation of using them for other CPUs with 2-way set associative L1 caches as well.
2000-06-06 21:41:07 +04:00
#if defined(MIPS3_5200)
#define MachFlushCache mips3_FlushCache_2way
#define MachFlushDCache mips3_FlushDCache_2way
#define MachHitFlushDCache mips3_HitFlushDCache_2way
#define MachFlushICache mips3_FlushICache_2way
Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast. Many thanks.
2000-03-19 22:16:13 +03:00
#else
Final changes for configuring MIPS1 and MIPS3 in a single kernel. * cpuregs.h: rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx. Add compile-time MIPS3-only, compile-time MIPS1-only, and runtime (both) definitions for number of TLB ASIDs (tlb pids) and shift count to extract a TLB pid. * locore.h: Delete unused vector slot for indexed TLB writes. mips1 and mips3 TLBs are different enough that we have to break them out at the caller anyway. * Add compile-time MIPS3-only andcompile-time MIPS1-only macros to call locore functions directly by name. Use the existing method table only if * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c: Use MIPS3_ or MIPS1_ specific names for TLB pids in mips3 and mips1 specific code paths (e.g., creating the kernel stack for process 0). Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 07:17:37 +04:00
#define MachFlushCache mips3_FlushCache
Changes for NetBSD/hpcmips. Support VR4100. Support 16KB page. Support CPU without FPU. Fix virtual alias problem(physio() case). [new options] options MIPS3_4100 /* VR4100 core */ options MIPS_16K_PAGE /* enable kernel support for 16k pages */ options SOFTFLOAT /* No FPU; avoid touching FPU registers */
1999-09-25 04:00:37 +04:00
#if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100)
#define MachFlushDCache mips3_FlushDCache /* VR4100 */
* Create mips_reg_t data type to allow register size to be decoupled from long or int or long long. Define macros in asm.h to facilitate choosing these on a port by port basis. * Create <machine/pubassym.h> mechanism to allow jmp_buf structure size to be calculated at system build time. * Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae for the architecture. For 64-bit oriented systems set the Status Register to allow 64-bit instructions. * Remove UADDR related macros because kernel U structure is now mapped normally. * Separate cpu.h into cpu.h and cpuarch.h to keep things neat. * Add support for QED 52xx processors
1999-01-14 21:45:45 +03:00
#elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT)
Final changes for configuring MIPS1 and MIPS3 in a single kernel. * cpuregs.h: rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx. Add compile-time MIPS3-only, compile-time MIPS1-only, and runtime (both) definitions for number of TLB ASIDs (tlb pids) and shift count to extract a TLB pid. * locore.h: Delete unused vector slot for indexed TLB writes. mips1 and mips3 TLBs are different enough that we have to break them out at the caller anyway. * Add compile-time MIPS3-only andcompile-time MIPS1-only macros to call locore functions directly by name. Use the existing method table only if * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c: Use MIPS3_ or MIPS1_ specific names for TLB pids in mips3 and mips1 specific code paths (e.g., creating the kernel stack for process 0). Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 07:17:37 +04:00
#define MachFlushDCache mips3_FlushDCache
* Create mips_reg_t data type to allow register size to be decoupled from long or int or long long. Define macros in asm.h to facilitate choosing these on a port by port basis. * Create <machine/pubassym.h> mechanism to allow jmp_buf structure size to be calculated at system build time. * Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae for the architecture. For 64-bit oriented systems set the Status Register to allow 64-bit instructions. * Remove UADDR related macros because kernel U structure is now mapped normally. * Separate cpu.h into cpu.h and cpuarch.h to keep things neat. * Add support for QED 52xx processors
1999-01-14 21:45:45 +03:00
#else
#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
#endif
Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast. Many thanks.
2000-03-19 22:16:13 +03:00
#define MachHitFlushDCache mips3_HitFlushDCache
Final changes for configuring MIPS1 and MIPS3 in a single kernel. * cpuregs.h: rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx. Add compile-time MIPS3-only, compile-time MIPS1-only, and runtime (both) definitions for number of TLB ASIDs (tlb pids) and shift count to extract a TLB pid. * locore.h: Delete unused vector slot for indexed TLB writes. mips1 and mips3 TLBs are different enough that we have to break them out at the caller anyway. * Add compile-time MIPS3-only andcompile-time MIPS1-only macros to call locore functions directly by name. Use the existing method table only if * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c: Use MIPS3_ or MIPS1_ specific names for TLB pids in mips3 and mips1 specific code paths (e.g., creating the kernel stack for process 0). Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 07:17:37 +04:00
#define MachFlushICache mips3_FlushICache
Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast. Many thanks.
2000-03-19 22:16:13 +03:00
#endif
Final changes for configuring MIPS1 and MIPS3 in a single kernel. * cpuregs.h: rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx. Add compile-time MIPS3-only, compile-time MIPS1-only, and runtime (both) definitions for number of TLB ASIDs (tlb pids) and shift count to extract a TLB pid. * locore.h: Delete unused vector slot for indexed TLB writes. mips1 and mips3 TLBs are different enough that we have to break them out at the caller anyway. * Add compile-time MIPS3-only andcompile-time MIPS1-only macros to call locore functions directly by name. Use the existing method table only if * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c: Use MIPS3_ or MIPS1_ specific names for TLB pids in mips3 and mips1 specific code paths (e.g., creating the kernel stack for process 0). Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 07:17:37 +04:00
#define MachSetPID mips3_SetPID
- Implement mips3_TBIAP(). - Remove obsoluted routines in locore_mips3.S - addiu -> addu, andi -> and, ori -> or.
2000-04-12 05:05:34 +04:00
#define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries)
#define MIPS_TBIS mips3_TBIS
Final changes for configuring MIPS1 and MIPS3 in a single kernel. * cpuregs.h: rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx. Add compile-time MIPS3-only, compile-time MIPS1-only, and runtime (both) definitions for number of TLB ASIDs (tlb pids) and shift count to extract a TLB pid. * locore.h: Delete unused vector slot for indexed TLB writes. mips1 and mips3 TLBs are different enough that we have to break them out at the caller anyway. * Add compile-time MIPS3-only andcompile-time MIPS1-only macros to call locore functions directly by name. Use the existing method table only if * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c: Use MIPS3_ or MIPS1_ specific names for TLB pids in mips3 and mips1 specific code paths (e.g., creating the kernel stack for process 0). Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 07:17:37 +04:00
#define MachTLBUpdate mips3_TLBUpdate
Make sure wbflush symbol treated as a C function call.
1999-11-12 09:17:13 +03:00
#define wbflush() mips3_wbflush()
Final changes for configuring MIPS1 and MIPS3 in a single kernel. * cpuregs.h: rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx. Add compile-time MIPS3-only, compile-time MIPS1-only, and runtime (both) definitions for number of TLB ASIDs (tlb pids) and shift count to extract a TLB pid. * locore.h: Delete unused vector slot for indexed TLB writes. mips1 and mips3 TLBs are different enough that we have to break them out at the caller anyway. * Add compile-time MIPS3-only andcompile-time MIPS1-only macros to call locore functions directly by name. Use the existing method table only if * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c: Use MIPS3_ or MIPS1_ specific names for TLB pids in mips3 and mips1 specific code paths (e.g., creating the kernel stack for process 0). Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 07:17:37 +04:00
#define proc_trampoline mips3_proc_trampoline
#endif
#if !defined(MIPS3) && defined (MIPS1)
#define MachFlushCache mips1_FlushCache
#define MachFlushDCache mips1_FlushDCache
#define MachFlushICache mips1_FlushICache
#define MachSetPID mips1_SetPID
- Implement mips3_TBIAP(). - Remove obsoluted routines in locore_mips3.S - addiu -> addu, andi -> and, ori -> or.
2000-04-12 05:05:34 +04:00
#define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries)
#define MIPS_TBIS mips1_TBIS
Final changes for configuring MIPS1 and MIPS3 in a single kernel. * cpuregs.h: rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx. Add compile-time MIPS3-only, compile-time MIPS1-only, and runtime (both) definitions for number of TLB ASIDs (tlb pids) and shift count to extract a TLB pid. * locore.h: Delete unused vector slot for indexed TLB writes. mips1 and mips3 TLBs are different enough that we have to break them out at the caller anyway. * Add compile-time MIPS3-only andcompile-time MIPS1-only macros to call locore functions directly by name. Use the existing method table only if * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c: Use MIPS3_ or MIPS1_ specific names for TLB pids in mips3 and mips1 specific code paths (e.g., creating the kernel stack for process 0). Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 07:17:37 +04:00
#define MachTLBUpdate mips1_TLBUpdate
Make sure wbflush symbol treated as a C function call.
1999-11-12 09:17:13 +03:00
#define wbflush() mips1_wbflush()
Final changes for configuring MIPS1 and MIPS3 in a single kernel. * cpuregs.h: rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx. Add compile-time MIPS3-only, compile-time MIPS1-only, and runtime (both) definitions for number of TLB ASIDs (tlb pids) and shift count to extract a TLB pid. * locore.h: Delete unused vector slot for indexed TLB writes. mips1 and mips3 TLBs are different enough that we have to break them out at the caller anyway. * Add compile-time MIPS3-only andcompile-time MIPS1-only macros to call locore functions directly by name. Use the existing method table only if * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c: Use MIPS3_ or MIPS1_ specific names for TLB pids in mips3 and mips1 specific code paths (e.g., creating the kernel stack for process 0). Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 07:17:37 +04:00
#define proc_trampoline mips1_proc_trampoline
#endif
#if defined(MIPS3) && defined (MIPS1)
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
#define MachFlushCache (*(mips_locore_jumpvec.flushCache))
#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
#define MachFlushICache (*(mips_locore_jumpvec.flushICache))
#define MachSetPID (*(mips_locore_jumpvec.setTLBpid))
Have mips_locoresw[] of 3 entry pointer array for different implementation of locore routines between MIPS1 and MIPS3. It's independent from mips_locore_jumpvec_t which is for cache/TLB manipulating routines peculiar to processor designs. mips_locore_jumpvec_t will be replaced with "processor closures" encapsulating implementation parameters (cpuinfo) and pointers to conventaion routines (cpuops), eventually.
2000-05-10 05:34:13 +04:00
#define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries)
#define MIPS_TBIS (*(mips_locore_jumpvec.TBIS))
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
#define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate))
Make MIPS1+MIPS3 compile again.
2000-03-23 17:49:29 +03:00
#define MachHitFlushDCache mips3_HitFlushDCache
Have mips_locoresw[] of 3 entry pointer array for different implementation of locore routines between MIPS1 and MIPS3. It's independent from mips_locore_jumpvec_t which is for cache/TLB manipulating routines peculiar to processor designs. mips_locore_jumpvec_t will be replaced with "processor closures" encapsulating implementation parameters (cpuinfo) and pointers to conventaion routines (cpuops), eventually.
2000-05-10 05:34:13 +04:00
#define wbflush() (*(mips_locore_jumpvec.wbflush))()
#define proc_trampoline (mips_locoresw[1])
Final changes for configuring MIPS1 and MIPS3 in a single kernel. * cpuregs.h: rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx. Add compile-time MIPS3-only, compile-time MIPS1-only, and runtime (both) definitions for number of TLB ASIDs (tlb pids) and shift count to extract a TLB pid. * locore.h: Delete unused vector slot for indexed TLB writes. mips1 and mips3 TLBs are different enough that we have to break them out at the caller anyway. * Add compile-time MIPS3-only andcompile-time MIPS1-only macros to call locore functions directly by name. Use the existing method table only if * mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c: Use MIPS3_ or MIPS1_ specific names for TLB pids in mips3 and mips1 specific code paths (e.g., creating the kernel stack for process 0). Add `options MIPS3' to pmax/conf/GENERIC.
1997-06-22 07:17:37 +04:00
#endif
Have mips_locoresw[] of 3 entry pointer array for different implementation of locore routines between MIPS1 and MIPS3. It's independent from mips_locore_jumpvec_t which is for cache/TLB manipulating routines peculiar to processor designs. mips_locore_jumpvec_t will be replaced with "processor closures" encapsulating implementation parameters (cpuinfo) and pointers to conventaion routines (cpuops), eventually.
2000-05-10 05:34:13 +04:00
#define CPU_IDLE (mips_locoresw[2])
* Create mips_reg_t data type to allow register size to be decoupled from long or int or long long. Define macros in asm.h to facilitate choosing these on a port by port basis. * Create <machine/pubassym.h> mechanism to allow jmp_buf structure size to be calculated at system build time. * Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae for the architecture. For 64-bit oriented systems set the Status Register to allow 64-bit instructions. * Remove UADDR related macros because kernel U structure is now mapped normally. * Separate cpu.h into cpu.h and cpuarch.h to keep things neat. * Add support for QED 52xx processors
1999-01-14 21:45:45 +03:00
/* cpu_switch_resume is called inside locore.S */
Garbage-collect redundant declarations: mips/include/locore.h: Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here. mips/include/cpu.h: remove cpu_prid definition. pmax/pmax/machdep.c: remove local protoypes of HitFlushDCache() functions. mips/mips/vm_machdep.c, mips/mips/vm_machdep.c:: remove local protoypes of HitFlushDCache() functions.
1997-06-16 13:50:26 +04:00
/*
* CPU identification, from PRID register.
*/
convert PRID handling to use macros on an int, not bit-fields. there's no reason to use bit-fields, and they just complexity to the header.
2000-07-27 21:29:05 +04:00
typedef int mips_prid_t;
Garbage-collect redundant declarations: mips/include/locore.h: Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here. mips/include/cpu.h: remove cpu_prid definition. pmax/pmax/machdep.c: remove local protoypes of HitFlushDCache() functions. mips/mips/vm_machdep.c, mips/mips/vm_machdep.c:: remove local protoypes of HitFlushDCache() functions.
1997-06-16 13:50:26 +04:00
convert PRID handling to use macros on an int, not bit-fields. there's no reason to use bit-fields, and they just complexity to the header.
2000-07-27 21:29:05 +04:00
#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff)
#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff)
#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff)
#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f)
#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f)
Garbage-collect redundant declarations: mips/include/locore.h: Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here. mips/include/cpu.h: remove cpu_prid definition. pmax/pmax/machdep.c: remove local protoypes of HitFlushDCache() functions. mips/mips/vm_machdep.c, mips/mips/vm_machdep.c:: remove local protoypes of HitFlushDCache() functions.
1997-06-16 13:50:26 +04:00
Yet more merging: * Move declaration of locore communcation variables (CPU family, cache sizes, etc) to mips/include/locore.h. Delete from pmax/include/cpu.h and older versions from pica/include/cpu.h. * Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu. * Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.
1997-06-16 10:17:25 +04:00
#ifdef _KERNEL
/*
* Global variables used to communicate CPU type, and parameters
* such as cache size, from locore to higher-level code (e.g., pmap).
*/
convert PRID handling to use macros on an int, not bit-fields. there's no reason to use bit-fields, and they just complexity to the header.
2000-07-27 21:29:05 +04:00
extern mips_prid_t cpu_id;
extern mips_prid_t fpu_id;
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
extern int cpu_arch;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>. Adds (most) support for ARC platform to port-independent mips code. Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by comparison to the OpenBSD 2.1 codebase of Soda's ARC port. Open issues: * Still no support for r4600 or mipsIV CPUs with two-way L1 cache. Code derived from Per Fogelstrom's OpenBSD source doesn't work on mips3 pmaxes with L2 cache. * Still some port-specific #ifdefs, for interrupt enable and pmax L2 cache-size. Needs more thought, but overlaps with work-in-progress by Tohru and Tsubai on spl()s and related stuff.
1998-09-11 20:46:31 +04:00
extern int mips_num_tlb_entries;
extern u_int mips_L1DCacheSize;
extern u_int mips_L1ICacheSize;
extern u_int mips_L1DCacheLSize;
extern u_int mips_L1ICacheLSize;
extern int mips_L2CachePresent;
More merged mips1/mips3 support: Remove cpu-specific routines from locore.S and add them to locore_r2000.S and locore_r4000.S. Add entries in locore jump vector table for switch_exit() and the cpu_switch() context resume. Add offsets into the jump vector to genassym.cf for use in locore.S.
1997-06-19 10:31:14 +04:00
extern u_int mips_L2CacheLSize;
extern u_int mips_CacheAliasMask;
Make pmap_prefer() use a global setting based on cache size instead of assuming 64KB. This allows best fit and will support bigger caches.
2000-07-20 22:33:40 +04:00
extern u_int mips_CachePreferMask;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>. Adds (most) support for ARC platform to port-independent mips code. Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by comparison to the OpenBSD 2.1 codebase of Soda's ARC port. Open issues: * Still no support for r4600 or mipsIV CPUs with two-way L1 cache. Code derived from Per Fogelstrom's OpenBSD source doesn't work on mips3 pmaxes with L2 cache. * Still some port-specific #ifdefs, for interrupt enable and pmax L2 cache-size. Needs more thought, but overlaps with work-in-progress by Tohru and Tsubai on spl()s and related stuff.
1998-09-11 20:46:31 +04:00
#ifdef MIPS3
extern int mips3_L1TwoWayCache;
extern int mips3_cacheflush_bug;
#endif /* MIPS3 */
Define C structures (struct kernframe, struct trapframe) for kernel-to-user trapframe. Use C structs in genassym.cf.
1999-02-27 05:54:05 +03:00
/*
Nuke register and remove trailling white space.
1999-04-24 12:01:01 +04:00
* trapframe argument passed to trap()
Define C structures (struct kernframe, struct trapframe) for kernel-to-user trapframe. Use C structs in genassym.cf.
1999-02-27 05:54:05 +03:00
*/
struct trapframe {
mips_reg_t tf_regs[17];
mips_reg_t tf_ra;
mips_reg_t tf_sr;
mips_reg_t tf_mullo;
mips_reg_t tf_mulhi;
mips_reg_t tf_epc; /* may be changed by trap() call */
};
/*
* Stack frame for kernel traps. four args passed in registers.
* A trapframe is pointed to by the 5th arg, and a dummy sixth argument
* is used to avoid alignment problems
*/
struct kernframe {
register_t cf_args[4 + 1];
register_t cf_pad; /* (for 8 word alignment) */
register_t cf_sp;
register_t cf_ra;
struct trapframe cf_frame;
};
Yet more merging: * Move declaration of locore communcation variables (CPU family, cache sizes, etc) to mips/include/locore.h. Delete from pmax/include/cpu.h and older versions from pica/include/cpu.h. * Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu. * Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.
1997-06-16 10:17:25 +04:00
#endif
Define the conventional pmax locore entry-point names to be calls through an vector (struct) of function pointers. Add prototype declarations for each vector entry. Add declarations for the r2000 (MIPS-I) and r4000 (MIPS-III) locore versions of the relevant functions.
1996-05-19 05:32:56 +04:00
#endif /* _MIPS_LOCORE_H */
Reference in New Issue Copy Permalink