misson20000
014ccfb94a
Aarch64 add thread registers ( #834 )
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* add thread registers to AArch64
* update bindings to add AArch64 thread registers
* fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 14:42:49 +07:00
Ryan Hileman
187b470245
add arm64 CPACR_EL1 register support ( #814 )
2017-05-02 14:51:19 +08:00
zhangwm
2e973a13f0
arm64eb: add support for ARM64 big endian.
2017-04-24 23:30:01 +08:00
Nguyen Anh Quynh
e917c9de10
Merge branch 'master' into msvc2
2017-04-21 01:17:00 +08:00
bunnei
4eca426fb6
unicorn_aarch64: Expose UC_ARM64_REG_NZCV register. ( #791 )
2017-03-31 10:21:45 +08:00
Nguyen Anh Quynh
c01dcf0a14
fix merge conflicts
2017-03-10 21:04:33 +08:00
stevielavern
b3a5eae81c
uc_reg_read & uc_reg_write now support ARM64 Neon registers ( #774 )
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* uc_reg_read & uc_reg_write now support ARM64 Neon registers
* Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
2017-03-07 21:29:34 +08:00
xorstream
8e45102b43
Arm support ported. ( #736 )
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* Fix for MIPS issue.
* Sparc support added.
* M68K support added.
* Arm support ported.
* Fix issue with VS2015 shlobj.h file
2017-01-23 23:30:57 +08:00
xorstream
1aeaf5c40d
This code should now build the x86_x64-softmmu part 2.
2017-01-19 22:50:28 +11:00
Elton G
47150b6df3
reg_read and reg_write now work with registers W0 through W30 in Aarch64 ( #716 )
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* reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton
* Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30)
Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write
* Fixed WRITE_DWORD macro
reg_write would zero out the high order bits when writing to 32 bit registers
e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
2017-01-15 20:13:35 +08:00
Chris Eagle
fccbcfd4c2
revert to use of g_free to make future qemu integrations easier ( #695 )
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* revert to use of g_free to make future qemu integrations easier
* bracing
2016-12-21 22:28:36 +08:00
Chris Eagle
e46545f722
remove glib dependency by provide compatible replacements
2016-12-18 14:56:58 -08:00
Nguyen Anh Quynh
b7cdbe7a88
Merge branch 'feat/reg_save_restore' of https://github.com/rhelmot/unicorn into rhelmot-feat/reg_save_restore
2016-10-07 09:57:07 +08:00
Ryan Hileman
cb615fdba7
remove uc->cpus
2016-09-23 07:38:21 -07:00
Andrew Dutcher
0ef2b5fd71
New feature: registers can be bulk saved/restored in an opaque blob
2016-08-20 04:14:07 -07:00
Nguyen Anh Quynh
cc6cbc5cf7
Merge branch 'memleak' into m2
2016-04-18 12:48:13 +08:00
Ryan Hileman
acd88856e1
add batched reg access
2016-04-04 20:51:38 -07:00
Nguyen Anh Quynh
fb1ebac000
Merge branch 'master' into m1
2016-03-09 15:13:42 +08:00
Hiroyuki UEKAWA
c5888e5670
move macros in qemu/target-*/unicorn*.c to uc_priv.h
2016-03-02 12:43:02 +09:00
Hiroyuki UEKAWA
1cd3c3093b
fix WRITE_BYTE_H
2016-03-02 10:51:50 +09:00
Nguyen Anh Quynh
20b01a6933
fix merge conflict
2016-02-01 12:08:38 +08:00
danghvu
36e53ad8a1
Fix arm & arm64 memleaks
2016-01-31 16:22:20 -06:00
Nguyen Anh Quynh
5a04bcb115
allow to change PC during callback. this solves issue #210
2016-01-28 14:06:17 +08:00
Nguyen Anh Quynh
c1dd9fbfdf
arm64: handle SP register. this fixes issue #122
2015-09-08 08:40:42 +08:00
Nguyen Anh Quynh
84e3b5c897
cast all the values to write to registers in uc_reg_write() to unsigned type. this fixes issue #98
2015-09-04 11:17:08 +08:00
Jonathon Reinhart
622d5cd5f9
change uch to uc_struct (target-arm)
2015-08-26 09:02:16 -04:00
Jonathon Reinhart
9163bba812
restore mode of .[ch] files
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These were marked as executable in 5c3b6819http://stackoverflow.com/q/1580596/119527
2015-08-24 21:19:12 -04:00
Chris Eagle
5c3b681945
Add const to uc_reg_write and derivitives
2015-08-24 09:42:50 -07:00
mothran
a167f7c456
renames the register constants so unicorn and capstone can compile together
2015-08-23 21:36:33 -07:00
Nguyen Anh Quynh
344d016104
import
2015-08-21 15:04:50 +08:00
