Parker Thompson
053ecd7bf4
Added ARM coproc registers ( #684 )
...
* Added ARM coproc registers
* Added regression test for vfp
2017-01-25 11:56:19 +08:00
Nguyen Anh Quynh
e4c7c3dbe4
cleanup Sparc unused code
2017-01-23 12:33:39 +08:00
Nguyen Anh Quynh
55d472c62c
cleanup Monitor related code
2017-01-23 00:53:31 +08:00
Nguyen Anh Quynh
b3faed1df9
cleanup
2017-01-23 00:30:13 +08:00
Nguyen Anh Quynh
a95fdbc5aa
cleanup qemu/include/exec/memory.h
2017-01-22 23:21:47 +08:00
Nguyen Anh Quynh
5de0785a1b
cleanup qemu/memory.c
2017-01-22 23:07:17 +08:00
Nguyen Anh Quynh
d04cc8671d
cleanup qemu/configure
2017-01-22 05:56:37 +08:00
Nguyen Anh Quynh
2a1b9d8e1b
cleanup qemu/Makefile.objs
2017-01-21 21:50:12 +08:00
Nguyen Anh Quynh
45717c61ba
cleanup qemu/util/qemu-timer-common.c
2017-01-21 14:53:33 +08:00
Nguyen Anh Quynh
647c97ddc3
ffs() is redundant
2017-01-21 11:11:22 +08:00
Nguyen Anh Quynh
fa12120d75
termios.h & strings.h are not needed
2017-01-21 11:02:17 +08:00
Nguyen Anh Quynh
ac68745a9c
we dont need to handle VGA & Migration memories
2017-01-20 17:03:39 +08:00
Nguyen Anh Quynh
fff532fc20
timer is redundant
2017-01-20 16:46:58 +08:00
Nguyen Anh Quynh
6daa8581cd
win32_start_routine() looks broken. TODO
2017-01-20 16:12:49 +08:00
xorstream
ee294eebb0
Fixed double free in win32 threads and changed free() to g_free(). ( #722 )
2017-01-20 16:03:35 +08:00
Nguyen Anh Quynh
c6de7930c9
remove mutex code
2017-01-20 15:44:03 +08:00
Nguyen Anh Quynh
42771848d6
no more spinlock
2017-01-20 14:57:33 +08:00
Nguyen Anh Quynh
a7fca49f7a
delete qemu/include/qemu/notify.h
2017-01-20 14:47:41 +08:00
Nguyen Anh Quynh
b887c3bb25
delete qemu/include/exec/poison.h
2017-01-20 13:58:50 +08:00
Nguyen Anh Quynh
94e55f45c1
del qemu/target-m68k/m68k-semi.c
2017-01-20 11:52:31 +08:00
Nguyen Anh Quynh
b678512fc1
remove kvm stuffs
2017-01-20 01:03:59 +08:00
Nguyen Anh Quynh
7e2234237c
del qemu/scripts/dump-guest-memory.py
2017-01-19 20:56:07 +08:00
Nguyen Anh Quynh
b9b82591a1
cleanup
2017-01-19 18:07:30 +08:00
Nguyen Anh Quynh
8a5b12c6f9
more cleanup in qemu/include/hw/
2017-01-19 15:20:06 +08:00
Nguyen Anh Quynh
287e047fdb
delete sparc32_dma.h & arm-semi.c
2017-01-19 15:10:41 +08:00
Nguyen Anh Quynh
f4f756e6dd
cleanup qemu/include/qemu/module.h
2017-01-19 15:00:25 +08:00
Nguyen Anh Quynh
7789a06d2d
cleanup qemu/default-configs/
2017-01-19 14:52:30 +08:00
Nguyen Anh Quynh
86e5d29b74
more cleanup qemu/configure
2017-01-19 14:15:00 +08:00
Nguyen Anh Quynh
f2691b0107
more cleanup qemu/configure
2017-01-19 14:11:54 +08:00
Nguyen Anh Quynh
37410d02f1
cleanup qemu/configure
2017-01-19 14:02:50 +08:00
Nguyen Anh Quynh
9735c6e28e
cleanup qemu/include/elf.h
2017-01-19 13:46:17 +08:00
Nguyen Anh Quynh
a6fa35430a
del qemu/include/qapi/opts-visitor.h
2017-01-19 13:23:48 +08:00
Nguyen Anh Quynh
d836ec62fc
del qemu/include/hw/irq.h
2017-01-19 13:14:15 +08:00
Nguyen Anh Quynh
0640b35943
mips: remove qemu/hw/mips/mips_int.c
2017-01-19 13:07:28 +08:00
Nguyen Anh Quynh
a154b251e3
cleanup
2017-01-19 12:18:46 +08:00
Nguyen Anh Quynh
326a9a5fba
cleanup qemu docs
2017-01-18 15:23:40 +08:00
Elton G
47150b6df3
reg_read and reg_write now work with registers W0 through W30 in Aarch64 ( #716 )
...
* reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton
* Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30)
Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write
* Fixed WRITE_DWORD macro
reg_write would zero out the high order bits when writing to 32 bit registers
e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
2017-01-15 20:13:35 +08:00
Nguyen Anh Quynh
7512ff57de
more cleanup
2017-01-10 16:29:47 +08:00
Nguyen Anh Quynh
c1f39c3db2
cleanup qemu/util code
2017-01-10 12:57:12 +08:00
Nguyen Anh Quynh
af165d254c
clean all qobject json code
2017-01-09 16:09:53 +08:00
Nguyen Anh Quynh
16894fdb6c
cleanup some qemu/util code
2017-01-09 15:48:21 +08:00
Nguyen Anh Quynh
52cb0ba78e
cleanup more synchronization code
2017-01-09 14:05:39 +08:00
Nguyen Anh Quynh
d7ead1135d
cleanup
2017-01-09 13:28:28 +08:00
Nguyen Anh Quynh
ffa97dc2a1
cleanup qemu/configure
2017-01-08 01:35:19 +08:00
Agustin Gianni
a63a34bfbc
Allow the client to write to CPSR
2017-01-05 00:00:15 +01:00
Nguyen Anh Quynh
2e8fa1dbf6
glib_compat: add guint64 type
2017-01-02 01:24:54 +08:00
Nguyen Anh Quynh
3fa50fc06a
macro GPOINTER_TO_UINT
2017-01-02 01:00:11 +08:00
Nguyen Anh Quynh
d5f513cbfe
Merge branch 'master' into noglib2
2016-12-27 22:49:59 +08:00
cojocar
428cb83060
Support for MCLASS ARM cpu (Cortex-M3) ( #700 )
...
Support for Cortex-M ARM CPU already exists in Qemu. This patch just
exposes a "cortex-m3" CPU.
"uc_open(UC_ARCH_ARM, UC_MODE_THUMB | UC_MODE_MCLASS, &uc);"
Instantiates a CPU with this feature on.
Signed-off-by: Lucian Cojocar <lucian@cojocar.com>
2016-12-27 22:49:06 +08:00
Nguyen Anh Quynh
3fb078c555
glib_compat: add COPYING_GLIB
2016-12-27 10:15:08 +08:00
