Support for MCLASS ARM cpu (Cortex-M3) (#700)
Support for Cortex-M ARM CPU already exists in Qemu. This patch just exposes a "cortex-m3" CPU. "uc_open(UC_ARCH_ARM, UC_MODE_THUMB | UC_MODE_MCLASS, &uc);" Instantiates a CPU with this feature on. Signed-off-by: Lucian Cojocar <lucian@cojocar.com>
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@ -13,7 +13,7 @@
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// These are masks of supported modes for each cpu/arch.
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// They should be updated when changes are made to the uc_mode enum typedef.
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#define UC_MODE_ARM_MASK (UC_MODE_ARM|UC_MODE_THUMB|UC_MODE_LITTLE_ENDIAN)
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#define UC_MODE_ARM_MASK (UC_MODE_ARM|UC_MODE_THUMB|UC_MODE_LITTLE_ENDIAN|UC_MODE_MCLASS)
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#define UC_MODE_MIPS_MASK (UC_MODE_MIPS32|UC_MODE_MIPS64|UC_MODE_LITTLE_ENDIAN|UC_MODE_BIG_ENDIAN)
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#define UC_MODE_X86_MASK (UC_MODE_16|UC_MODE_32|UC_MODE_64|UC_MODE_LITTLE_ENDIAN)
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#define UC_MODE_PPC_MASK (UC_MODE_PPC64|UC_MODE_BIG_ENDIAN)
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@ -19,8 +19,11 @@
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static int tosa_init(struct uc_struct *uc, MachineState *machine)
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{
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//cpu_arm_init(uc, "pxa255");
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uc->cpu = (CPUState *)cpu_arm_init(uc, "cortex-a15"); // FIXME
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if (uc->mode & UC_MODE_MCLASS) {
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uc->cpu = (CPUState *)cpu_arm_init(uc, "cortex-m3");
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} else {
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uc->cpu = (CPUState *)cpu_arm_init(uc, "cortex-a15");
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}
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return 0;
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}
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