mirrors/unicorn
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
1,886 Commits 9 Branches 27 Tags 47 MiB
68eb357984
Commit Graph

99 Commits

Author SHA1 Message Date
Chen Huitao
68eb357984 fix some oss-fuzz bugs (#1180) 
* fix oss-fuzz 10419.

* fix oss-fuzz 10427.

* fix oss-fuzz 10421.

* fix oss-fuzz 10422.

* fix oss-fuzz 10425.

* fix oss-fuzz 10426.

* fix oss-fuzz 10426.

* fix oss-fuzz 10422.

* fix oss-fuzz  10426.

* fix oss-fuzz 10456.

* fix oss-fuzz 10428.

* fix oss-fuzz 10429.

* fix oss-fuzz 10431.

* fix oss-fuzz 10435.

* fix oss-fuzz 10430.

* fix oss-fuzz 10436.

* remove unused var.
 2020-01-04 23:42:02 +08:00
Charles Ferguson
99097cab4c Add implementation of access to the ARM SPSR register. (#1178) 
The SPSR register is named within the Unicorn headers, but the code
to access it is absent. This means that it will always read as 0 and
ignore writes. This makes it harder to work with changes in processor
mode, as the usual way to return from a CPU exception is a
`MOVS pc, lr` for undefined instructions or `SUBS pc, lr, #4`
for most other aborts - which implicitly restores the CPSR from SPSR.

This change adds the access to the SPSR so that it can be read and
written as the caller might expect.
 2020-01-02 09:42:01 +08:00
Chen Huitao
ca6516ff79 Remove warnings (#1140) 
* remove warnings on windows with vs2019.

* remove warnings.
 2019-09-08 16:44:16 +08:00
yhql
3185128031 Add ARM MSP, PSP and CONTROL register access (#1071) 
Necessary for NVIC exception emulation from user.
 2019-03-07 08:37:27 +08:00
cfrantz
6c319941a5 Add support for the ARM IPSR register. (#1067) 
1. Create an enum name for the IPSR register.
2. Implement read and write of the IPSR via the xpsr helper functions.

Fixes #1065
 2019-02-28 09:55:27 +08:00
Catena cyber
400a0ab309 Uses latest qemu arm thumb load store stuff (#1021) 2018-09-27 10:32:48 +08:00
Nguyen Anh Quynh
86313650f9 fix some gcc warnings 2018-07-25 12:38:15 +08:00
Nguyen Anh Quynh
d5f83a9c2e arm: cleanup for ARM_CPU 2017-12-21 09:43:33 +08:00
Nguyen Anh Quynh
e67be36c88 arm: remove unused variable in arm_cpu_get_phys_page_debug() 2017-12-20 22:12:35 +08:00
misson20000
014ccfb94a Aarch64 add thread registers (#834) 
* add thread registers to AArch64

* update bindings to add AArch64 thread registers

* fix indentation for register read/write switch-case in unicorn_aarch64.c
 2017-05-14 14:42:49 +07:00
Ryan Hileman
ae6ea3b91d fix arm64 hang (fix #827) (#828) 2017-05-09 20:19:32 +08:00
zhangwm
4a62409949 arm64eb: arm64 big endian also using little endian instructions. (#816) 
* arm64eb: arm64 big endian also using little endian instructions.

* arm64: using another example that depends on endians.

example:
1. store a word: 0x12345678
2. load a byte:
   * little endian : 0x78
   * big endian    : 0x12
 2017-05-04 20:00:48 +08:00
Ryan Hileman
1b00d3f89a remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
Ryan Hileman
187b470245 add arm64 CPACR_EL1 register support (#814) 2017-05-02 14:51:19 +08:00
zhangwm
2e973a13f0 arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
Nguyen Anh Quynh
513075e061 arm: fix an warning reported by GCC 2017-04-21 21:12:57 +08:00
Nguyen Anh Quynh
e917c9de10 Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
0xSeb
605400e10e determine correct Thumb/Thumb2 instruction size (16/32-bit) for code … (#796) 
* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook

* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook

* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook
 2017-04-15 00:39:56 +08:00
bunnei
4eca426fb6 unicorn_aarch64: Expose UC_ARM64_REG_NZCV register. (#791) 2017-03-31 10:21:45 +08:00
Nguyen Anh Quynh
094ca80092 fix conflicts 2017-03-30 12:23:24 +08:00
zhangwm
ccdb0ff523 armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition. 2017-03-15 22:25:35 +08:00
zhangwm
d8fe34a2e8 armeb: Add support for ARM big endian. 2017-03-13 22:32:44 +08:00
Nguyen Anh Quynh
c01dcf0a14 fix merge conflicts 2017-03-10 21:04:33 +08:00
feliam
0150ca24b1 Add support for ARM application flags - APSR register (#776) 2017-03-09 22:28:03 +08:00
stevielavern
b3a5eae81c uc_reg_read & uc_reg_write now support ARM64 Neon registers (#774) 
* uc_reg_read & uc_reg_write now support ARM64 Neon registers

* Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
 2017-03-07 21:29:34 +08:00
Nguyen Anh Quynh
6ea39f7d5a merge msvc with master 2017-02-24 10:39:36 +08:00
Nguyen Anh Quynh
714cf2c609 arm: fix a warning 2017-02-23 20:32:09 +08:00
Parker Thompson
053ecd7bf4 Added ARM coproc registers (#684) 
* Added ARM coproc registers

* Added regression test for vfp
 2017-01-25 11:56:19 +08:00
xorstream
e08d1bf7c6 Arm issue fix. (#738) 
* Fix for MIPS issue.

* Sparc support added.

* M68K support added.

* Arm support ported.

* Fix issue with VS2015 shlobj.h file

* Arm issue fix.
 2017-01-24 17:45:01 +08:00
xorstream
8e45102b43 Arm support ported. (#736) 
* Fix for MIPS issue.

* Sparc support added.

* M68K support added.

* Arm support ported.

* Fix issue with VS2015 shlobj.h file
 2017-01-23 23:30:57 +08:00
Nguyen Anh Quynh
206819bd98 cleanup after msvc port 2017-01-22 21:27:17 +08:00
xorstream
770c5616e2 Automated leading tab to spaces conversion. 2017-01-21 12:28:22 +11:00
xorstream
429bfca48e Fixes for MSVC native support to still work with GCC/GNU. 2017-01-21 01:07:10 +11:00
xorstream
fac6a66860 platform.h move #3 2017-01-21 00:13:21 +11:00
xorstream
92392e0f57 Merge with current master. 2017-01-20 18:22:28 +11:00
Nguyen Anh Quynh
b678512fc1 remove kvm stuffs 2017-01-20 01:03:59 +08:00
xorstream
1aeaf5c40d This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
Nguyen Anh Quynh
287e047fdb delete sparc32_dma.h & arm-semi.c 2017-01-19 15:10:41 +08:00
Elton G
47150b6df3 reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716) 
* reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton

* Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30)
Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write

* Fixed WRITE_DWORD macro

reg_write would zero out the high order bits when writing to 32 bit registers

e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
 2017-01-15 20:13:35 +08:00
Agustin Gianni
a63a34bfbc Allow the client to write to CPSR 2017-01-05 00:00:15 +01:00
Chris Eagle
fccbcfd4c2 revert to use of g_free to make future qemu integrations easier (#695) 
* revert to use of g_free to make future qemu integrations easier

* bracing
 2016-12-21 22:28:36 +08:00
Chris Eagle
f8f9e993a8 merge upstream/noglib and update some glib related types 2016-12-19 12:32:06 -08:00
Chris Eagle
e07e57a862 battling git 2016-12-19 12:10:02 -08:00
Chris Eagle
71bda8e012 stick to gint/guint rather than int32_t/uint32_t 2016-12-19 09:43:35 -08:00
Nguyen Anh Quynh
bd1632e60c fix an warning 'control may reach end of non-void function' 2016-12-20 00:21:02 +08:00
Chris Eagle
e46545f722 remove glib dependency by provide compatible replacements 2016-12-18 14:56:58 -08:00
Nguyen Anh Quynh
b7cdbe7a88 Merge branch 'feat/reg_save_restore' of https://github.com/rhelmot/unicorn into rhelmot-feat/reg_save_restore 2016-10-07 09:57:07 +08:00
Nguyen Anh Quynh
7d15a60b25 arm64: disable deadcode introduced by PR #643 2016-09-29 12:34:44 +08:00
Nguyen Anh Quynh
507d557aa5 arm: disable deadcode introduced by PR #643 2016-09-29 12:33:16 +08:00
Ryan Hileman
cb615fdba7 remove uc->cpus 2016-09-23 07:38:21 -07:00