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Add support for ARM application flags - APSR register (#776)

This commit is contained in:
feliam 2017-03-09 11:28:03 -03:00 committed by Nguyen Anh Quynh
parent 2749b8412e
commit 0150ca24b1
2 changed files with 8 additions and 1 deletions
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3
bindings/python/sample_arm.py
View File

@ -41,7 +41,8 @@ def test_arm():
mu.reg_write(UC_ARM_REG_R0, 0x1234)
mu.reg_write(UC_ARM_REG_R2, 0x6789)
mu.reg_write(UC_ARM_REG_R3, 0x3333)
mu.reg_write(UC_ARM_REG_APSR, 0xFFFFFFFF) #All application flags turned on
# tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block)

6
qemu/target-arm/unicorn_arm.c
View File

@ -62,6 +62,9 @@ int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
*(float64 *)value = ARM_CPU(uc, mycpu)->env.vfp.regs[regid - UC_ARM_REG_D0];
else {
switch(regid) {
case UC_ARM_REG_APSR:
*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV;
break;
case UC_ARM_REG_CPSR:
*(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env);
break;
@ -107,6 +110,9 @@ int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, i
ARM_CPU(uc, mycpu)->env.vfp.regs[regid - UC_ARM_REG_D0] = *(float64 *)value;
else {
switch(regid) {
case UC_ARM_REG_APSR:
cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, CPSR_NZCV);
break;
case UC_ARM_REG_CPSR:
cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, ~0);
break;