Commit Graph

27 Commits

Author SHA1 Message Date
lazymio
9427f0a553
Merge pull request #1991 from apparentlymart/b-riscv-invalidinsn-pcadj
riscv: Invalid 32-bit instruction should not decrement pc
2024-09-21 18:26:59 +08:00
Jose Martins
58f1a612e8 target/riscv: fix wfi exception behavior
The wfi exception trigger behavior should take into account user mode,
hstatus.vtw, and the fact the an wfi might raise different types of
exceptions depending on various factors:

If supervisor mode is not present:

- an illegal instruction exception should be generated if user mode
executes and wfi instruction and mstatus.tw = 1.

If supervisor mode is present:

- when a wfi instruction is executed, an illegal exception should be triggered
if either the current mode is user or the mode is supervisor and mstatus.tw is
set.

Plus, if the hypervisor extensions are enabled:

- a virtual instruction exception should be raised when a wfi is executed from
virtual-user or virtual-supervisor and hstatus.vtw is set.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420213656.85148-1-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-09-03 13:44:55 -07:00
Martin Atkins
ac1b37421d riscv: Invalid 32-bit instruction should not decrement pc
This line appears to be trying to undo the effect of adding 4 to pc above,
but does so incorrectly and so ends up returning with next_pc earlier than
it was prior to decoding.

This causes the translator to malfunction because it does not expect
pc_next to decrease during decoding: this is effectively reporting that
the invalid construction has a negative size, which is impossible. The
decoder uses the increase in next_pc to decide the translation block size,
but converts it to uint16_t thereby causing a block containing _only_ an
invalid instruction to be treated as having size 65532 (reinterpreted -4)
and therefore the translation loop tries to find the next translation block
at 65532 bytes after the invalid instruction, which can cause a spurious
instruction access/page fault if the page containing that address is not
mapped as executable.

In practice we don't need to readjust the pc at all here because it is
correct to report that the invalid instruction is four bytes long. This
allows the translation loop to correctly find the next instruction, and
to avoid producing spurious TLB fills that might cause incorrect exceptions.
2024-08-28 14:06:17 -07:00
Robert Xiao
30d202b89e Simplify reg_read/reg_write, obtaining a perf boost.
Single reg_read/reg_write is now about 25% faster.
2023-06-16 15:23:42 -07:00
Robert Xiao
074566cf69 Slight refactoring to reduce code duplication.
This also comes with a performance bump due to inlining of reg_read/reg_write
(as they're only called once now) and the unlikely() on CHECK_REG_TYPE.
2023-06-16 15:23:42 -07:00
Robert Xiao
4055a5ab10 Implement uc_reg_{read,write}{,_batch}2 APIs.
These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.

Completes #1831.
2023-06-16 15:23:42 -07:00
Takacs, Philipp
e96ac42b2e Remove MMU hacks
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.

The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d add virtuall tlb
this virtuall tlb allows to use mmu indipendent of the architectur
2023-03-28 13:50:11 +02:00
Takacs, Philipp
b7b1a4d6b4 difference between stop_request and quit_request
quit_request is for internal use. This means the IP register was updated and
qemu needs to rebuild the translation blocks.

stop_request is set by the user (uc_emu_stop) to indecate that unicorn sould
stop emulating.
2023-03-07 14:38:49 +01:00
lazymio
9167ab8671
Set riscv_get_pc for uc->get_pc 2022-05-21 00:02:22 +02:00
lazymio
345b63ee96
Only exit TB if pc is within the memory range 2022-05-07 00:16:31 +02:00
mio
085ee07c73
No more hard-coded cpu models 2021-12-30 01:05:10 +01:00
lazymio
87a391d549
Inline uc_tracecode when there is only exactly one hook 2021-11-21 16:44:39 +01:00
lazymio
640251e1aa
Leave out size parameter in callback 2021-11-09 00:21:34 +01:00
lazymio
c6fdbb3735
Add RISCV CSR registers 2021-11-07 20:36:04 +01:00
lazymio
613ddf0985
Format 2021-11-04 19:58:44 +01:00
lazymio
172a2fbe6d
Support changing cpu model for riscv 2021-11-04 19:13:53 +01:00
lazymio
09aa0f944f
Merge QDucasse:riscv_extension_d
Fix and close #1469

Fix test for riscv float points

Fix the riscv cpu config we left out
2021-11-03 13:20:46 +01:00
lazymio
bcf85be86d
Add a new hook type UC_HOOK_TCG_OPCODE 2021-11-03 01:46:24 +01:00
lazymio
3dd2e0f95d
Basic implementation of uc_ctl 2021-11-01 00:39:36 +01:00
lazymio
e62b0ef255
Add clang-format and format code to qemu code style 2021-10-29 12:44:49 +02:00
lazymio
e695686c15
Remove AFL Integration by reverting 2021-10-26 11:22:21 +02:00
lazymio
7ac7c23c12
Fix Windows build for AFL integration 2021-10-25 16:11:58 +02:00
lazymio
1fa2eb688b
Fix UC_MODE_AFL and update config 2021-10-25 14:39:40 +02:00
lazymio
dd7476a9bd
Initial import unicornafl 2021-10-25 00:51:16 +02:00
mio
567bd08b86
Update riscv pc and fix #1465 2021-10-19 23:22:13 +02:00
Nguyen Anh Quynh
aaaea14214 import Unicorn2 2021-10-03 22:14:44 +08:00