Commit Graph

614 Commits

Author SHA1 Message Date
lazymio
c1106b811b
Fix a memory leak in mmio 2021-11-16 22:44:03 +01:00
lazymio
fc467edbc6
Fix 32bit target getting wrong offset for mmio 2021-11-16 22:40:57 +01:00
lazymio
247ffbe0e8
Support nested uc_emu_start calls 2021-11-16 21:07:03 +01:00
lazymio
43c643d4af
Fix #1488 2021-11-16 09:41:21 +01:00
lazymio
7e244f87b4
Fix UC_HOOK_EDGE_GENERATED implementation 2021-11-11 22:15:15 +01:00
lazymio
23ef5da491
Merge pull request #1481 from bet4it/cp15
Restore cp15 registers
2021-11-09 16:50:31 +01:00
Bet4
acaed986b5 Restore cp15 registers 2021-11-09 13:13:08 +08:00
lazymio
640251e1aa
Leave out size parameter in callback 2021-11-09 00:21:34 +01:00
lazymio
2f61592ff9
Fix uc_mem_protect 2021-11-07 20:37:58 +01:00
lazymio
c6fdbb3735
Add RISCV CSR registers 2021-11-07 20:36:04 +01:00
George Hotz
7268c2a19b
mips: support reading and writing of hi/lo regs 2021-11-07 20:27:02 +01:00
lazymio
94a82ed94d
Ensure JIT protection is disabled when generating TB 2021-11-07 20:23:25 +01:00
lazymio
613ddf0985
Format 2021-11-04 19:58:44 +01:00
lazymio
871de4ad65
Split mips cpu to 32 and 64 2021-11-04 19:58:32 +01:00
lazymio
0555095388
Support changing cpu model for ppc 2021-11-04 19:53:02 +01:00
lazymio
e5a2eae173
Add comment for default cpu model 2021-11-04 19:22:50 +01:00
lazymio
64452e249d
Support changing cpu model for sparc 2021-11-04 19:22:08 +01:00
lazymio
b0280f5e55
Support changing cpu model for m68k 2021-11-04 19:16:35 +01:00
lazymio
172a2fbe6d
Support changing cpu model for riscv 2021-11-04 19:13:53 +01:00
lazymio
435ac71f47
Support changing cpu model for x86 2021-11-04 19:10:29 +01:00
lazymio
837c3be347
Support changing cpu model for MIPS 2021-11-04 19:05:56 +01:00
lazymio
dfbffa44ec
Support changing cpu model for ARM 2021-11-04 18:37:10 +01:00
lazymio
3e4b4af7d3
Support change page size 2021-11-04 17:03:30 +01:00
lazymio
3ead1731fe
Also instrument sub2
In this case, users don't need to care about the stuble difference inside tcg opcode
2021-11-03 23:48:09 +01:00
lazymio
67e2386da6
Add test and close #1477 2021-11-03 21:40:13 +01:00
lazymio
6b5529fcb7
Merge pull request #1458 from bet4it/patch
Port some patches from Unicorn1 to Unicorn2
2021-11-03 20:59:42 +01:00
lazymio
9818840f4e
Add tests for UC_HOOK_TCG_OPCODE 2021-11-03 20:56:45 +01:00
lazymio
09aa0f944f
Merge QDucasse:riscv_extension_d
Fix and close #1469

Fix test for riscv float points

Fix the riscv cpu config we left out
2021-11-03 13:20:46 +01:00
lazymio
bcf85be86d
Add a new hook type UC_HOOK_TCG_OPCODE 2021-11-03 01:46:24 +01:00
lazymio
eb75d459f0
Add a regression test for invalidating empty TB and have a better solution 2021-11-03 01:07:06 +01:00
Bet4
aaf340d9e4 Merge branch 'dev' into patch 2021-11-02 18:36:22 +08:00
lazymio
c11b9aa5c3
Add a new hook type UC_HOOK_EDGE_GENERATED and corresponding sample 2021-11-01 23:27:35 +01:00
lazymio
b7e82d460c
Expose more TB related stuff 2021-11-01 22:11:43 +01:00
lazymio
6c3960242b
Format unicorn_arm and unicorn_aarch64 2021-11-01 10:17:58 +01:00
lazymio
0a3e46bf4f
Format 2021-11-01 09:41:25 +01:00
lazymio
3dd2e0f95d
Basic implementation of uc_ctl 2021-11-01 00:39:36 +01:00
lazymio
84abf1d3a4
A stronger test and handle addr_end = 0 2021-10-31 21:01:55 +01:00
lazymio
4bcf1c4a7c
Flush TB at exit with a better approach instead of flushing tlb in uc1 2021-10-31 19:43:56 +01:00
lazymio
e62b0ef255
Add clang-format and format code to qemu code style 2021-10-29 12:44:49 +02:00
lazymio
e695686c15
Remove AFL Integration by reverting 2021-10-26 11:22:21 +02:00
lazymio
7ac7c23c12
Fix Windows build for AFL integration 2021-10-25 16:11:58 +02:00
lazymio
1fa2eb688b
Fix UC_MODE_AFL and update config 2021-10-25 14:39:40 +02:00
lazymio
d965c0f159
Use UCLOG and fix uc_afl_fuzz 2021-10-25 10:46:52 +02:00
lazymio
dd7476a9bd
Initial import unicornafl 2021-10-25 00:51:16 +02:00
mio
567bd08b86
Update riscv pc and fix #1465 2021-10-19 23:22:13 +02:00
Bet4
c400924fe1
Merge branch 'dev' into patch 2021-10-17 18:18:09 +08:00
mio
6d0d0897f8
Fix Rust build and CI.
Add a test for ppc and fix ppc on windows.
2021-10-17 02:11:38 +02:00
Sven Almgren
f27c6fa655 X86 instruction FTST was incorrectly overwriting ST0 instead of FT0 (#1372)
* X86 instruction FTST was incorrectly overwriting ST0 instead of FT0

* credits update
2021-10-12 08:41:57 +08:00
Bet4
5f40667d91 Support querying architecture mode besides arm (#1389) 2021-10-11 11:39:23 +08:00
David CARLIER
e2a924a32b qemu_getauxval FreeBSD implementation backport (#1366) 2021-10-11 11:22:16 +08:00