Commit Graph

19 Commits

Author SHA1 Message Date
Michael Matz
bde802df29 x86-asm: Reorganize instr_type
Disjoint instruction types don't need to be a bit field, so
introduce an enumeration (3 bits).  Also the 0x0f prefix can
be expressed by a bit, doesn't need a byte in the opcode field.
That enables to encode further prefixes still in 16 bit.
To not have to touch all insns do some macro fiddling filtering
out a 0x0f byte in the second position.
2016-12-15 17:47:05 +01:00
Michael Matz
ed35ac841b x86-asm: Add more SSE2 instructions
In particular those that are extensions of existing mmx (or sse1)
instructions by a simple 0x66 prefix.  There's one caveat for
x86-64: as we don't yet correctly handle the 0xf3 prefix
the movq mem64->xmm is wrong (tested in asmtest.S).  Needs
some refactoring of the instr_type member.
2016-12-15 17:47:05 +01:00
Michael Matz
f2a4cb0a0e x86-asm: Reject some invalid arith imm8 instruction
There were two errors in the arithmetic imm8 instruction.  They accept
only REGW, and in case the user write a xxxb opcode that variant
needs to be rejected as well (it's not automatically rejected by REGW
in case the destination is memory).
2016-05-16 05:10:21 +02:00
Michael Matz
4f27e217a8 x86-asm: Fix signed constants and opcode order
Two things: negative constants were rejected (e.g. "add $-15,%eax").
Second the insn order was such that the arithmetic IM8S forms
weren't used (always the IM32 ones).  Switching them prefers those
but requires a fix for size calculation in case the opcodes were
OPC_ARITH and OPC_WLX (whose size starts with 1, not zero).
2016-05-14 04:33:41 +02:00
Michael Matz
080ec9fadd x86-asm: Consolidate insn descriptions
Use OPC_BWLX and OPC_WLX in i386-asm.h and x86_64-asm.h to
reduce number of differences between both.
2016-05-14 04:05:34 +02:00
Michael Matz
6bd8c936e3 x86-64-asm: Add mov[sz]xq opcodes
This adds the zero/sign-extending opcodes with 64bit destinations.
2016-05-12 00:57:02 +02:00
Michael Matz
b9f01dffc6 x86-64-asm: Clean up 64bit immediate support
Fix it to actually be able to parse 64bit immediates (enlarge
operand value type).  Then, generally there's no need for accepting
IM64 anywhere, except in the 0xba+r mov opcodes, so OP_IM is
unnecessary, as is OPT_IMNO64.  Improve the generated code a bit
by preferring the 0xc7 opcode for im32->reg64, instead of the
im64->reg64 form (which we therefore hardcode).
2016-05-11 23:47:02 +02:00
Michael Matz
613962e353 x86-64 asm: Remove useless jmp opcode
Also remove the hacky mod/rm byte emission during
disp/imm writing.
2016-05-11 18:56:19 +02:00
Michael Matz
bd93dc6923 x86: Improve cmov handling
cmov can accept multi sizes, but is also a OPC_TEST opcode,
deal with this.
2016-05-11 18:54:24 +02:00
Michael Matz
5e47b08dc8 [x86] Fix some asm problems
A bag of assembler fixes, to be either compatible with GAS
(e.g. order of 'test' operands), accept more instructions,
count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes
on x86_64 to not use %rip relative addressing mode, to not use
invalid insns in tests/asmtest.S for x86_64.

Result is that now output of GAS and of tcc on tests/asmtest.S
is mostly the same.
2016-05-09 23:17:47 +02:00
Michael Matz
78ee3759b8 x86-asm: Fix lcall/ljmp, xchg and inc/dec
Various x86 asm fixes: 64bit lcall/ljmp like 32bit a commit before,
xchgw accepted wrong operands on 32 and 64bit, and 64bit used
0x40/0x48+reg for incw/decw, but those are REX prefixes, not
instructions.
2016-05-03 01:16:43 +02:00
seyko
eb870b006c SSE opcodes to TCC assembler (i386, x86_64)
patch from Anaël Seghezzi
    a test program:
    ============================
    #include <stdio.h>
    struct fl4{ float x, y, z, w; };
    void asm_test(void)
    {
	struct fl4 v1, v2, v3;
	v1.x = 0.1;
	v1.y = 0.2;
	v1.z = 0.4;
	v1.w = 0.3;
	v2.x = 0.11;
	v2.y = 0.0;
	v2.z = 0.01;
	v2.w = 0.04;
	asm volatile (
	    "movups %0, %%xmm0;"
	    "movups %1, %%xmm1;"
	    "addps %%xmm1, %%xmm0;"
	    "movups %%xmm0, %2"
	:: "g" (v1), "g" (v2), "g" (v3) : "memory");
	printf("sse fl4 add : %f %f %f %f\n", v3.x, v3.y, v3.z, v3.w);
	printf("expected : %f %f %f %f\n", v1.x+v2.x, v1.y+v2.y, v1.z+v2.z, v1.w+v2.w);
    }
    int main() { asm_test(); }
    /*
	sse fl4 add : 0.210000 0.200000 0.410000 0.340000
	expected : 0.210000 0.200000 0.410000 0.340000
    */
    ============================
2015-09-23 14:58:06 +03:00
gus knight
89ad24e7d6 Revert all of my changes to directories & codingstyle. 2015-07-29 16:57:12 -04:00
gus knight
47e06c6d4e Reorganize the source tree.
* Documentation is now in "docs".
 * Source code is now in "src".
 * Misc. fixes here and there so that everything still works.

I think I got everything in this commit, but I only tested this
on Linux (Make) and Windows (CMake), so I might've messed
something up on other platforms...
2015-07-27 16:03:25 -04:00
seyko
e260b03686 Allow tcc to understand a setob,... opcodes as alias to seto,...
PS: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20101122/112576.html
This is fix PR8686 for llvm: accepting a 'b' suffix at the end
of all the setcc instructions.
2015-01-06 22:59:19 +03:00
Thomas Preud'homme
a1a691a030 Detect correct instruction with incorrect operands
Display a different warning when an instruction is recognized by tcc but
the operands found do not correspond to the constraints of the
instruction.
2013-09-24 15:37:11 +02:00
grischka
dd3d4f7295 x86-64: fix udiv, add cqto instruction 2009-12-19 22:16:19 +01:00
grischka
1383055b17 x86_64: fix asm 2009-11-14 21:48:37 +01:00
Frederic Feret
526c464504 first support of x86_64 assembly 2009-11-13 18:08:59 +01:00