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Commit Graph

39 Commits

Author SHA1 Message Date
Michael Matz
2d17e5a6c4 riscv64: adjust for cast changes
gfunc_call plays with types and needs to retain the unsignedness
now (this was a latent problem before commit 35475b5).
2019-12-17 00:48:57 +01:00
grischka
35475b5423 remove VT_LVAL_BYTE etc.
For some reason there was no point for that anymore.
2019-12-16 20:59:23 +01:00
grischka
5914f4d57d tccgen.c: cleanup reg classes
wrap some copy&paste code into functions
2019-12-16 20:44:48 +01:00
grischka
72729d8e36 allow libtcc states to be used concurrently
This allows creation of TCCStates and operation with API
calls independently from each other, even from threads.

Frontend (option parsing/libtcc.c) and backend (linker/tccelf.c)
now depend only on the TCCState (s1) argument.

Compilation per se (tccpp.c, tccgen.c) is still using
globals for convenience.  There is only one entry point
to this section which is tcc_compile() which is protected
by a semaphore.

There are some hacks involved to avoid too many changes,
as well as some changes in order to avoid too many hacks ;)

The test libtcc_test_mt.c shows the feature.  Except this
new file the patch adds 87 lines overall.
2019-12-11 02:36:19 +01:00
herman ten brugge
4461f38a9e Fix bounds checking for linux/windows 2019-12-10 08:07:25 +01:00
Michael Matz
91e297acd3 riscv: Optimize compares
don't convert to 1/0 prematurely, we can save enough info
in the VT_CMP metadata to be usable for the gtst branch expansion.
2019-09-01 23:13:21 +02:00
Michael Matz
48ba22c744 riscv: Replace RR insn emitter with specific one
instead of using o() directly.  Makes the code a little easier
to read.
2019-09-01 23:13:21 +02:00
Michael Matz
d5bb407cc4 riscv: Add special cases for const operands
RISC-V supports small immediates for some operations, let's
use them.
2019-09-01 23:13:21 +02:00
Michael Matz
f8d80464a9 riscv: factor load/store code
split out common code and tidy result.
2019-09-01 23:13:21 +02:00
Michael Matz
83cf5bf17f riscv: TLC of param passing
factor and cleanup the param passing code somewhat.
2019-09-01 23:13:21 +02:00
Michael Matz
c505074a9f riscv: rewrite parameter passing
this fixes the ret_mixed_test of abitest.c, now everything of the
testsuite works.

The generic code for returns is good enough for our use, except in
the specific case of a mixed int/float structures returned in registers,
so instead of duplicating the whole generic gfunc_return function, add
another modus for gfunc_sret: returning -1 makes the actual register
transfer by a new backend function.
2019-09-01 23:13:21 +02:00
Michael Matz
0cb6e3fff8 riscv: Fix mixed2 and mixed3 abi tests
this was caused by a simple bug, not by the current inability
to pass a {float,int} struct per psABI.  So now only ret_mixed_test
is still broken.
2019-09-01 23:13:21 +02:00
Michael Matz
98f1b83ffe riscv: Start fixing float struct passing/returnig
this fixes ret_2float_test, ret_2double_test and
ret_8plus2double_test of abitest.c.  The common gfunc_return
actually works for these cases, so let's use that for now.

The ret_mixed_test (as well as mixed2 and mixed3) are left
broken, and tccgen.c:gfunc_return can't be used for that as is,
so I'll leave the gfunc_return implementation in riscv64-gen.c for
now, I'll have to think about this some more.
2019-09-01 23:13:20 +02:00
Michael Matz
98dc4c123d riscv: Fix stdarg_many_test
if named params are passed on stack, the va_arg area begins after
that, not at sp+0.  Fixes abitest:stdarg_many_test.
2019-09-01 23:13:20 +02:00
Michael Matz
e9c2a1996a riscv: Fix tcctest.c
this is it!  With this tcctest.c works, as well as compiling
TCC with itself.  abitest.c doesn't yet work due to known
problems, all the rest does.  There are still warnings during
linking.
2019-09-01 23:13:20 +02:00
Michael Matz
1ada32900b riscv: Fix ftoi and ftof(long double->float)
float to int must be truncations, not normal rounding.
And ftof was typoed to select the wrong conversion function.

This fixes tcctest.c completely.  (make -C tests test1)
2019-09-01 23:13:20 +02:00
Michael Matz
06184aec53 riscv: fix relocs for global syms
loads and stores to global symbols need to go via the
GOT (at least for weaks), otherwise -run doesn't work.
Ideally we'd generate GOT relocs (and loads) always and replace
them with PCREL relocs and adds during linking.
2019-09-01 23:13:20 +02:00
Michael Matz
69c77d1597 riscv: Fix unsigned 32bit loads
the invariant for the risc-v codegen is, that 64bit regs
generally contain the sign-extension of a 32bit value.
This wasn't heeded by loads of 32bit values from memory, which
used lwu and ultimately caused a miscompilation in string_test
of tcctest.c.

Now most of tcctest.c works (not with -run, but with linking
a real executable), except some ftoi/ftof conversions.
2019-09-01 23:13:20 +02:00
Michael Matz
2668eda595 riscv: Implement long double support
for the implementation of operations we can reuse the ones
from lib/lib-arm64.c, risc-v long double is also float128.
Also implement ggoto, and PDIV, and use t0 in load/store as
temporary register if necessary, not one given by get_reg
(the latter can destroy assignments of long double parameters
in function calls that are already set up).

This let's us compile tcc.c and tcctest.c, though both
don't yet work.
2019-09-01 23:13:20 +02:00
Michael Matz
2616c6b230 riscv: Fix 73_arm.c
some constants were loaded wrong (e.g. 0xffffabcdU), and
risc-v needs to do explicit zero-extensions for widening from
32bit (not sign-extensions like the other 64bit targets).

This makes the whole tests2.all testsuite work.

Parameter passing is still not psABI-compliant, but internally
consistent.  (e.g. structs of two floats/doubles are passed
in integer registers, but should sit in float regs).
2019-09-01 23:13:20 +02:00
Michael Matz
982de78e8d riscv: implement stdarg functions
this also fixes passing of params > 16 bytes.  In riscv
they aren't passed by value on stack, but via reference (and
because callees are allowed to modify by-ref params the caller must
allocate an own copy per call).

This fixes the stdarg parts of 73_arm.c.
2019-09-01 23:13:20 +02:00
Michael Matz
f44df9d85b riscv: some work on large function arguments
like long double (16 bytes) and structs.  Not completely
correct, but 73_arm64 somewhat works now (when the stdarg part
is disabled), though with some errors.  What's definitely incorrect
is arguments of a mixed int/float struct.  I'm using VT_LDOUBLE
(which conveniently has to be placed in a int-reg-pair) to load/store
structure arguments of size > 8 and <= 16, and that can lead to
overreads.
2019-09-01 23:13:20 +02:00
Michael Matz
ddb0c2de92 riscv: support large stack and far jumps
for 101_cleanup we need 256kb stack (with the associated problem
of needing a larger prologue/epilogue) as well as jumps out of
range for the 21bit offsets (exactly for second part of the prologue).
2019-09-01 23:13:19 +02:00
Michael Matz
b69c2ea2cf riscv: fix 90_struct-init
indirect calls were broken.
2019-09-01 23:13:19 +02:00
Michael Matz
31ecaa7c28 riscv: GOT loads, signed remainder, ELF flags
* support loading sym addresses from GOT: important for weak syms,
  fixes 104_inline.  This is still incomplete, it only works
  for taking the sym address, not for directly loading/storing into
  such symbols (i.e. not for VT_LVAL)
* another op: '%'
* ELF flags: add EF_RISCV_FLOAT_ABI_DOUBLE, which is our ABI.
2019-09-01 23:13:19 +02:00
Michael Matz
5390a729d9 riscv: Implement VLA stuff
makes 78_vla_label and 79_vla_continue work.
2019-09-01 23:13:19 +02:00
Michael Matz
9164594d1f riscv: load 64bit constants, and 32bit shifts
fixes 95_bitfields.  loading 64bit constants is suboptimal
right now.  int32_t shifts really need to use the W form,
otherwise 'x << 24 >> 24' doesn't extract the low 8 bits.
2019-09-01 23:13:19 +02:00
Michael Matz
215bc1aab4 riscv: Add sar, shr insn
fixes 92_enum_bitfield.
2019-09-01 23:13:19 +02:00
Michael Matz
f64d460d29 riscv: fix 72_long_long_constant
32bit signed constants larger than 0x7ffff800 were handled wrongly.
2019-09-01 23:13:19 +02:00
Michael Matz
9309585dbe riscv: some long double support
long double on risc-v is 128bit, but there are no registers
for that type (without the Q ISA extension).  They are passed
like two 64bit integers values (with an exception for varargs,
where it's an aligned register pair).  This all requires some
hacks in generic code as otherwise RC_FLOAT regs are tried for
holding values of long double type, but we need a RC_INT register
pair.  This really could all use some cleanup for all archs.

This doesn't implement any conversions of operations for long
double, but it's enough to get 70_floating_point_literals working.
2019-09-01 23:13:19 +02:00
Michael Matz
9c1b17407f riscv: Make 32_leds work
* more ops: umod and udiv
* large immediates: suboptimal code, e.g. when loading
  0xffffffffU (which is what a cast from long to int does).

tests2 work up to 67_macro_concat.
2019-09-01 23:13:19 +02:00
Michael Matz
02c8e69a07 riscv: fp parameters
makes 23_type_coercion work.  (clean up to 31_args)
2019-09-01 23:13:19 +02:00
Michael Matz
0d3db83f16 riscv: float ops
* compares
* add/sub/mul/div
* float-float converts

makes 22_floating_point work.
2019-09-01 23:13:19 +02:00
Michael Matz
9214087259 riscv: More insns, operands and arg slots
* load/store of FP ops
* load/store from symbols, VT_LLOCAL, some with large addend
* load of VT_JMP result
* calls with many args (stack slots)
* calls with FP args
* more operations: and/or/xor/div
2019-09-01 23:13:19 +02:00
Michael Matz
b1c7520886 riscv: more insns
* register indirect loads and stores
* load of local addresses
* indirect calls (uses ra as temporary reg if necessary)
* operations *, -, <<
* gen_cvt_sxtw: is not needed in most cases, let's see

tests2 runs until (incl) 09_do_while.
2019-09-01 23:13:18 +02:00
Michael Matz
16edda58b7 riscv: Add more ops and fixes
* implement compares, gtst and gsym/gjmp and add
* implement stores (simple cases)
* fix arg passing with more than one register arg, fix
  loads to not always use 8byte loads
* add some predefined macros: __riscv, __riscv_xlen,
  __SIZEOF_POINTER__ (needed by glibc header)

The first 5 tests of tests2 run now.
2019-09-01 23:13:08 +02:00
Michael Matz
ef7c1a4e96 riscv: Implement some loads and calls
so that a hello world works.
2019-08-14 18:22:18 +02:00
Michael Matz
35d7b5934e riscv: hacky prolog, epilog and return
this now allows to compile a simple working example:

  int main(void) { return 0; }
2019-08-14 18:22:14 +02:00
Michael Matz
0676d5bc23 riscv64: Add skeleton target 2019-08-14 18:18:46 +02:00