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https://github.com/frida/tinycc
synced 2025-02-10 04:14:02 +03:00
riscv: some long double support
long double on risc-v is 128bit, but there are no registers for that type (without the Q ISA extension). They are passed like two 64bit integers values (with an exception for varargs, where it's an aligned register pair). This all requires some hacks in generic code as otherwise RC_FLOAT regs are tried for holding values of long double type, but we need a RC_INT register pair. This really could all use some cleanup for all archs. This doesn't implement any conversions of operations for long double, but it's enough to get 70_floating_point_literals working.
This commit is contained in:
Michael Matz
parent
9c1b17407f
commit
9309585dbe
@ -345,24 +345,45 @@ ST_FUNC void gfunc_call(int nb_args)
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int i, align, size, aireg, afreg;
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int info[nb_args ? nb_args : 1];
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int stack_adj = 0, ofs;
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int force_stack = 0;
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SValue *sv;
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Sym *sa;
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aireg = afreg = 0;
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sa = vtop[-nb_args].type.ref->next;
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for (i = 0; i < nb_args; i++) {
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int *pareg;
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int *pareg, nregs, infreg = 0;
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sv = &vtop[1 + i - nb_args];
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sv->type.t &= ~VT_ARRAY; // XXX this should be done in tccgen.c
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size = type_size(&sv->type, &align);
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if (size > 8 || ((sv->type.t & VT_BTYPE) == VT_STRUCT))
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if ((size > 8 && ((sv->type.t & VT_BTYPE) != VT_LDOUBLE))
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|| ((sv->type.t & VT_BTYPE) == VT_STRUCT))
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tcc_error("unimp: call arg %d wrong type", nb_args - i);
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pareg = sa && is_float(sv->type.t) ? &afreg : &aireg;
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if (*pareg < 8) {
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info[i] = *pareg + (sa && is_float(sv->type.t) ? 8 : 0);
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nregs = 1;
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if ((sv->type.t & VT_BTYPE) == VT_LDOUBLE) {
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infreg = 0, nregs = 2;
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if (!sa) {
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aireg = (aireg + 1) & ~1;
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}
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} else
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infreg = sa && is_float(sv->type.t);
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pareg = infreg ? &afreg : &aireg;
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if ((*pareg < 8) && !force_stack) {
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info[i] = *pareg + (infreg ? 8 : 0);
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(*pareg)++;
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if (nregs == 1)
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;
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else if (*pareg < 8)
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(*pareg)++;
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else {
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info[i] |= 16;
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stack_adj += 8;
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tcc_error("unimp: param passing half in reg, half on stack");
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}
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} else {
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info[i] = 16;
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info[i] = 32;
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stack_adj += (size + align - 1) & -align;
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if (!sa)
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force_stack = 1;
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}
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if (sa)
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sa = sa->next;
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@ -371,7 +392,7 @@ ST_FUNC void gfunc_call(int nb_args)
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if (stack_adj) {
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EI(0x13, 0, 2, 2, -stack_adj); // addi sp, sp, -adj
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for (i = ofs = 0; i < nb_args; i++) {
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if (1 && info[i] >= 16) {
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if (1 && info[i] >= 32) {
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vrotb(nb_args - i);
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size = type_size(&vtop->type, &align);
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/* Once we support offseted regs we can do this:
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@ -393,9 +414,20 @@ ST_FUNC void gfunc_call(int nb_args)
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}
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for (i = 0; i < nb_args; i++) {
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int r = info[nb_args - 1 - i];
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if (r < 16) {
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if (r < 32) {
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r &= 15;
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vrotb(i+1);
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gv(r < 8 ? RC_R(r) : RC_F(r - 8));
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if (vtop->r2 < VT_CONST) {
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assert((vtop->type.t & VT_BTYPE) == VT_LDOUBLE);
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assert(vtop->r < 7);
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if (vtop->r2 != 1 + vtop->r) {
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/* XXX we'd like to have 'gv' move directly into
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the right class instead of us fixing it up. */
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EI(0x13, 0, ireg(vtop->r) + 1, ireg(vtop->r2), 0); // mv Ra+1, RR2
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vtop->r2 = 1 + vtop->r;
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}
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}
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vrott(i+1);
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}
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}
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38
tccgen.c
38
tccgen.c
@ -1548,6 +1548,11 @@ ST_FUNC int gv(int rc)
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if (vtop->r & VT_MUSTBOUND)
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gbound();
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#endif
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#ifdef TCC_TARGET_RISCV64
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/* XXX mega hack */
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if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE && rc == RC_FLOAT)
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rc = RC_INT;
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#endif
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r = vtop->r & VT_VALMASK;
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rc2 = (rc & RC_FLOAT) ? RC_FLOAT : RC_INT;
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@ -1568,7 +1573,10 @@ ST_FUNC int gv(int rc)
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if (r >= VT_CONST
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|| (vtop->r & VT_LVAL)
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|| !(reg_classes[r] & rc)
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#if PTR_SIZE == 8
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#ifdef TCC_TARGET_RISCV64
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|| ((vtop->type.t & VT_BTYPE) == VT_QLONG && (vtop->r2 >= NB_REGS || !(reg_classes[vtop->r2] & rc2)))
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|| ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE && (vtop->r2 >= NB_REGS || !(reg_classes[vtop->r2] & rc2)))
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#elif PTR_SIZE == 8
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|| ((vtop->type.t & VT_BTYPE) == VT_QLONG && !(reg_classes[vtop->r2] & rc2))
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|| ((vtop->type.t & VT_BTYPE) == VT_QFLOAT && !(reg_classes[vtop->r2] & rc2))
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#else
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@ -1577,7 +1585,10 @@ ST_FUNC int gv(int rc)
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)
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{
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r = get_reg(rc);
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#if PTR_SIZE == 8
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#ifdef TCC_TARGET_RISCV64
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if (((vtop->type.t & VT_BTYPE) == VT_QLONG) || ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE)) {
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int addr_type = VT_LLONG, load_size = 8, load_type = VT_LLONG;
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#elif PTR_SIZE == 8
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if (((vtop->type.t & VT_BTYPE) == VT_QLONG) || ((vtop->type.t & VT_BTYPE) == VT_QFLOAT)) {
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int addr_type = VT_LLONG, load_size = 8, load_type = ((vtop->type.t & VT_BTYPE) == VT_QLONG) ? VT_LLONG : VT_DOUBLE;
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#else
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@ -1708,6 +1719,9 @@ static int rc_fret(int t)
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if (t == VT_LDOUBLE) {
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return RC_ST0;
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}
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#elif defined TCC_TARGET_RISCV64
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if (t == VT_LDOUBLE)
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return RC_IRET;
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#endif
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return RC_FRET;
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}
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@ -1720,6 +1734,9 @@ static int reg_fret(int t)
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if (t == VT_LDOUBLE) {
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return TREG_ST0;
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}
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#elif defined TCC_TARGET_RISCV64
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if (t == VT_LDOUBLE)
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return REG_IRET;
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#endif
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return REG_FRET;
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}
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@ -1797,6 +1814,9 @@ static void gv_dup(void)
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if ((t & VT_BTYPE) == VT_LDOUBLE) {
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rc = RC_ST0;
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}
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#elif defined TCC_TARGET_RISCV64
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if ((t & VT_BTYPE) == VT_LDOUBLE)
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rc = RC_INT;
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#endif
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sv.type.t = t;
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}
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@ -3403,6 +3423,9 @@ ST_FUNC void vstore(void)
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} else if ((ft & VT_BTYPE) == VT_QFLOAT) {
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rc = RC_FRET;
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}
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#elif defined TCC_TARGET_RISCV64
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if (dbt == VT_LDOUBLE)
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rc = RC_INT;
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#endif
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}
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r = gv(rc); /* generate value */
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@ -3421,7 +3444,10 @@ ST_FUNC void vstore(void)
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vtop[-1].r = t | VT_LVAL;
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}
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/* two word case handling : store second register at word + 4 (or +8 for x86-64) */
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#if PTR_SIZE == 8
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#ifdef TCC_TARGET_RISCV64
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if (dbt == VT_QLONG || dbt == VT_LDOUBLE) {
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int addr_type = VT_LLONG, load_size = 8, load_type = VT_LLONG;
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#elif PTR_SIZE == 8
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if (((ft & VT_BTYPE) == VT_QLONG) || ((ft & VT_BTYPE) == VT_QFLOAT)) {
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int addr_type = VT_LLONG, load_size = 8, load_type = ((vtop->type.t & VT_BTYPE) == VT_QLONG) ? VT_LLONG : VT_DOUBLE;
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#else
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@ -5743,6 +5769,9 @@ static void expr_cond(void)
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if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
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rc = RC_ST0;
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}
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#elif defined TCC_TARGET_RISCV64
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if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE)
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rc = RC_INT;
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#endif
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}
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gv(rc);
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@ -5914,6 +5943,9 @@ static void expr_cond(void)
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if ((type.t & VT_BTYPE) == VT_LDOUBLE) {
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rc = RC_ST0;
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}
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#elif defined TCC_TARGET_RISCV64
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if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE)
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rc = RC_INT;
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#endif
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} else if ((type.t & VT_BTYPE) == VT_LLONG) {
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/* for long longs, we use fixed registers to avoid having
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