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https://github.com/frida/tinycc
synced 2024-11-23 16:19:35 +03:00
riscv: Replace RR insn emitter with specific one
instead of using o() directly. Makes the code a little easier to read.
This commit is contained in:
Michael Matz
parent
d5bb407cc4
commit
48ba22c744
@ -101,6 +101,12 @@ static void EIu(uint32_t opcode, uint32_t func3,
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o(opcode | (func3 << 12) | (rd << 7) | (rs1 << 15) | (imm << 20));
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}
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static void ER(uint32_t opcode, uint32_t func3,
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uint32_t rd, uint32_t rs1, uint32_t rs2, uint32_t func7)
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{
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o(opcode | func3 << 12 | rd << 7 | rs1 << 15 | rs2 << 20 | func7 << 25);
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}
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static void EI(uint32_t opcode, uint32_t func3,
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uint32_t rd, uint32_t rs1, uint32_t imm)
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{
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@ -175,7 +181,7 @@ static int load_symofs(int r, SValue *sv, int forstore)
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if (((unsigned)fc + (1 << 11)) >> 12) {
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rr = is_ireg(r) ? ireg(r) : 5; // t0
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o(0x37 | (rr << 7) | ((0x800 + fc) & 0xfffff000)); //lui RR, upper(fc)
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o(0x33 | (rr << 7) | (rr << 15) | (8 << 20)); // add RR, RR, s0
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ER(0x33, 0, rr, rr, 8, 0); // add RR, RR, s0
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sv->c.i = fc << 20 >> 20;
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}
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} else
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@ -268,7 +274,7 @@ ST_FUNC void load(int r, SValue *sv)
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} else if (v < VT_CONST) { /* reg-reg */
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//assert(!fc); XXX support offseted regs
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if (is_freg(r) && is_freg(v))
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o(0x53 | (rr << 7) | (freg(v) << 15) | (freg(v) << 20) | ((bt == VT_DOUBLE ? 0x11 : 0x10) << 25)); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
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ER(0x53, 0, rr, freg(v), freg(v), bt == VT_DOUBLE ? 0x11 : 0x10); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
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else if (is_ireg(r) && is_ireg(v))
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EI(0x13, 0, rr, ireg(v), 0); // addi RR, V, 0 == mv RR, V
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else {
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@ -696,7 +702,7 @@ ST_FUNC void gfunc_epilog(void)
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d = 16;
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o(0x37 | (5 << 7) | ((0x800 + (v-16)) & 0xfffff000)); //lui t0, upper(v)
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EI(0x13, 0, 5, 5, (v-16) << 20 >> 20); // addi t0, t0, lo(v)
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o(0x33 | (2 << 7) | (2 << 15) | (5 << 20)); //add sp, sp, t0
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ER(0x33, 0, 2, 2, 5, 0); // add sp, sp, t0
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}
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EI(0x03, 3, 1, 2, d - 8 - num_va_regs * 8); // ld ra, v-8(sp)
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EI(0x03, 3, 8, 2, d - 16 - num_va_regs * 8); // ld s0, v-16(sp)
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@ -707,7 +713,7 @@ ST_FUNC void gfunc_epilog(void)
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EI(0x13, 0, 8, 2, d - num_va_regs * 8); // addi s0, sp, d
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o(0x37 | (5 << 7) | ((0x800 + (v-16)) & 0xfffff000)); //lui t0, upper(v)
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EI(0x13, 0, 5, 5, (v-16) << 20 >> 20); // addi t0, t0, lo(v)
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o(0x33 | (2 << 7) | (2 << 15) | (5 << 20) | (0x20 << 25)); //sub sp, sp, t0
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ER(0x33, 0, 2, 2, 5, 0x20); // sub sp, sp, t0
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gjmp_addr(func_sub_sp_offset + 5*4);
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}
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saved_ind = ind;
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@ -849,7 +855,7 @@ static void gen_opil(int op, int ll)
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if (fc)
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gen_opil('-', ll), a = ireg(vtop++->r);
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if (op == TOK_NE)
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o(0x33 | (3 << 12) | (ireg(d) << 7) | (0 << 15) | (a << 20)); // sltu d, x0, a == snez d,a
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ER(0x33, 3, ireg(d), 0, a, 0); //sltu d, x0, a == snez d,a
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else
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EI(0x13, 3, ireg(d), a, 1); // sltiu d, a, 1 == seqz d,a
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--vtop;
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@ -871,44 +877,44 @@ static void gen_opil(int op, int ll)
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tcc_error("implement me: %s(%s)", __FUNCTION__, get_tok_str(op, NULL));
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case '+':
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o(0x33 | (d << 7) | (a << 15) | (b << 20)); // add d, a, b
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ER(0x33, 0, d, a, b, 0); // add d, a, b
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break;
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case '-':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); //sub d, a, b
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ER(0x33, 0, d, a, b, 0x20); // sub d, a, b
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break;
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case TOK_SAR:
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o(0x33 | ll | (d << 7) | (a << 15) | (b << 20) | (5 << 12) | (1 << 30)); //sra d, a, b
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ER(0x33 | ll, 5, d, a, b, 0x20); // sra d, a, b
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break;
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case TOK_SHR:
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o(0x33 | ll | (d << 7) | (a << 15) | (b << 20) | (5 << 12)); //srl d, a, b
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ER(0x33 | ll, 5, d, a, b, 0); // srl d, a, b
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break;
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case TOK_SHL:
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (1 << 12)); //sll d, a, b
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ER(0x33, 1, d, a, b, 0); // sll d, a, b
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break;
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case '*':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25)); //mul d, a, b
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ER(0x33, 0, d, a, b, 1); // mul d, a, b
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break;
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case '/':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (4 << 12)); //div d, a, b
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ER(0x33, 4, d, a, b, 1); // div d, a, b
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break;
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case '&':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (7 << 12)); // and d, a, b
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ER(0x33, 7, d, a, b, 0); // and d, a, b
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break;
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case '^':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (4 << 12)); // xor d, a, b
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ER(0x33, 4, d, a, b, 0); // xor d, a, b
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break;
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case '|':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (6 << 12)); // or d, a, b
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ER(0x33, 6, d, a, b, 0); // or d, a, b
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break;
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case '%':
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (6 << 12)); //rem d, a, b
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ER(0x33, 6, d, a, b, 1); // rem d, a, b
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break;
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case TOK_UMOD:
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (7 << 12)); //remu d, a, b
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ER(0x33, 7, d, a, b, 1); // remu d, a, b
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break;
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case TOK_PDIV:
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case TOK_UDIV:
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (5 << 12)); //divu d, a, b
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ER(0x33, 5, d, a, b, 1); // divu d, a, b
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break;
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case TOK_ULT:
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@ -927,7 +933,7 @@ static void gen_opil(int op, int ll)
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int t = a; a = b; b = t;
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inv ^= 1;
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}
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (((op > TOK_UGT) ? 2 : 3) << 12)); // slt[u] d, a, b
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ER(0x33, (op > TOK_UGT) ? 2 : 3, d, a, b, 0); // slt[u] d, a, b
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if (inv)
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EI(0x13, 4, d, d, 1); // xori d, d, 1
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vset_VT_CMP(TOK_NE);
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@ -935,9 +941,9 @@ static void gen_opil(int op, int ll)
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break;
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case TOK_NE:
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case TOK_EQ:
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o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); // sub d, a, b
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ER(0x33, 0, d, a, b, 0x20); // sub d, a, b
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if (op == TOK_NE)
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o(0x33 | (3 << 12) | (d << 7) | (0 << 15) | (d << 20)); // sltu d, x0, d == snez d,d
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ER(0x33, 3, d, 0, d, 0); // sltu d, x0, d == snez d,d
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else
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EI(0x13, 3, d, d, 1); // sltiu d, d, 1 == seqz d,d
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vset_VT_CMP(TOK_NE);
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@ -1007,7 +1013,7 @@ ST_FUNC void gen_opf(int op)
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rd = get_reg(RC_FLOAT);
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vtop->r = rd;
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rd = freg(rd);
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o(0x53 | (rd << 7) | (rs1 << 15) | (rs2 << 20) | (7 << 12) | (dbl << 25) | (op << 27)); // fop.[sd] RD, RS1, RS2 (dyn rm)
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ER(0x53, 7, rd, rs1, rs2, dbl | (op << 2)); // fop.[sd] RD, RS1, RS2 (dyn rm)
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break;
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case '-':
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op = 1; // fsub
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@ -1024,7 +1030,7 @@ ST_FUNC void gen_opf(int op)
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rd = get_reg(RC_INT);
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vtop->r = rd;
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rd = ireg(rd);
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o(0x53 | (rd << 7) | (rs1 << 15) | (rs2 << 20) | (op << 12) | (dbl << 25) | (0x14 << 27)); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)
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ER(0x53, op, rd, rs1, rs2, dbl | 0x50); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)
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if (invert)
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EI(0x13, 4, rd, rd, 1); // xori RD, 1
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break;
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@ -1175,7 +1181,7 @@ ST_FUNC void gen_vla_alloc(CType *type, int align)
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int rr = ireg(gv(RC_INT));
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EI(0x13, 0, rr, rr, 15); // addi RR, RR, 15
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EI(0x13, 7, rr, rr, -16); // andi, RR, RR, -16
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o(0x33 | (2 << 7) | (2 << 15) | (rr << 20) | (0x20 << 25)); //sub sp, sp, rr
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ER(0x33, 0, 2, 2, rr, 0x20); // sub sp, sp, rr
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vpop();
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}
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#endif
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