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tinycc/riscv64-gen.c

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riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
#ifdef TARGET_DEFS_ONLY
// Number of registers available to allocator:
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
#define NB_REGS 19 // x10-x17 aka a0-a7, f10-f17 aka fa0-fa7, xxx, ra, sp
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
#define TREG_R(x) (x) // x = 0..7
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
#define TREG_F(x) (x + 8) // x = 0..7
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
// Register classes sorted from more general to more precise:
#define RC_INT (1 << 0)
#define RC_FLOAT (1 << 1)
#define RC_R(x) (1 << (2 + (x))) // x = 0..7
#define RC_F(x) (1 << (10 + (x))) // x = 0..7
#define RC_IRET (RC_R(0)) // int return register class
tccgen.c: cleanup reg classes wrap some copy&paste code into functions
2019-12-16 20:44:35 +03:00
#define RC_IRE2 (RC_R(1)) // int 2nd return register class
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
#define RC_FRET (RC_F(0)) // float return register class
#define REG_IRET (TREG_R(0)) // int return register number
tccgen.c: cleanup reg classes wrap some copy&paste code into functions
2019-12-16 20:44:35 +03:00
#define REG_IRE2 (TREG_R(1)) // int 2nd return register number
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
#define REG_FRET (TREG_F(0)) // float return register number
#define PTR_SIZE 8
#define LDOUBLE_SIZE 16
#define LDOUBLE_ALIGN 16
#define MAX_ALIGN 16
#define CHAR_IS_UNSIGNED
#else
allow libtcc states to be used concurrently This allows creation of TCCStates and operation with API calls independently from each other, even from threads. Frontend (option parsing/libtcc.c) and backend (linker/tccelf.c) now depend only on the TCCState (s1) argument. Compilation per se (tccpp.c, tccgen.c) is still using globals for convenience. There is only one entry point to this section which is tcc_compile() which is protected by a semaphore. There are some hacks involved to avoid too many changes, as well as some changes in order to avoid too many hacks ;) The test libtcc_test_mt.c shows the feature. Except this new file the patch adds 87 lines overall.
2019-12-11 02:37:18 +03:00
#define USING_GLOBALS
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
#include "tcc.h"
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
#include <assert.h>
#define XLEN 8
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
#define TREG_RA 17
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
#define TREG_SP 18
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
ST_DATA const int reg_classes[NB_REGS] = {
RC_INT | RC_R(0),
RC_INT | RC_R(1),
RC_INT | RC_R(2),
RC_INT | RC_R(3),
RC_INT | RC_R(4),
RC_INT | RC_R(5),
RC_INT | RC_R(6),
RC_INT | RC_R(7),
RC_FLOAT | RC_F(0),
RC_FLOAT | RC_F(1),
RC_FLOAT | RC_F(2),
RC_FLOAT | RC_F(3),
RC_FLOAT | RC_F(4),
RC_FLOAT | RC_F(5),
RC_FLOAT | RC_F(6),
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
RC_FLOAT | RC_F(7),
0,
1 << TREG_RA,
1 << TREG_SP
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
};
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
static int ireg(int r)
{
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
if (r == TREG_RA)
return 1; // ra
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
if (r == TREG_SP)
return 2; // sp
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
assert(r >= 0 && r < 8);
return r + 10; // tccrX --> aX == x(10+X)
}
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
static int is_ireg(int r)
{
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
return (unsigned)r < 8 || r == TREG_RA || r == TREG_SP;
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
}
static int freg(int r)
{
assert(r >= 8 && r < 16);
return r - 8 + 10; // tccfX --> faX == f(10+X)
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
}
static int is_freg(int r)
{
return r >= 8 && r < 16;
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
ST_FUNC void o(unsigned int c)
{
int ind1 = ind + 4;
if (nocode_wanted)
return;
if (ind1 > cur_text_section->data_allocated)
section_realloc(cur_text_section, ind1);
write32le(cur_text_section->data + ind, c);
ind = ind1;
}
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
static void EIu(uint32_t opcode, uint32_t func3,
uint32_t rd, uint32_t rs1, uint32_t imm)
{
o(opcode | (func3 << 12) | (rd << 7) | (rs1 << 15) | (imm << 20));
}
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
static void ER(uint32_t opcode, uint32_t func3,
uint32_t rd, uint32_t rs1, uint32_t rs2, uint32_t func7)
{
o(opcode | func3 << 12 | rd << 7 | rs1 << 15 | rs2 << 20 | func7 << 25);
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
static void EI(uint32_t opcode, uint32_t func3,
uint32_t rd, uint32_t rs1, uint32_t imm)
{
assert(! ((imm + (1 << 11)) >> 12));
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
EIu(opcode, func3, rd, rs1, imm);
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
}
static void ES(uint32_t opcode, uint32_t func3,
uint32_t rs1, uint32_t rs2, uint32_t imm)
{
assert(! ((imm + (1 << 11)) >> 12));
o(opcode | (func3 << 12) | ((imm & 0x1f) << 7) | (rs1 << 15)
| (rs2 << 20) | ((imm >> 5) << 25));
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
// Patch all branches in list pointed to by t to branch to a:
ST_FUNC void gsym_addr(int t_, int a_)
{
uint32_t t = t_;
uint32_t a = a_;
while (t) {
unsigned char *ptr = cur_text_section->data + t;
uint32_t next = read32le(ptr);
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
uint32_t r = a - t, imm;
if ((r + (1 << 21)) & ~((1U << 22) - 2))
tcc_error("out-of-range branch chain");
imm = (((r >> 12) & 0xff) << 12)
| (((r >> 11) & 1) << 20)
| (((r >> 1) & 0x3ff) << 21)
| (((r >> 20) & 1) << 31);
write32le(ptr, r == 4 ? 0x33 : 0x6f | imm); // nop || j imm
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
t = next;
}
}
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
static int load_symofs(int r, SValue *sv, int forstore)
{
static Sym label;
int rr, doload = 0;
int fc = sv->c.i, v = sv->r & VT_VALMASK;
if (sv->r & VT_SYM) {
assert(v == VT_CONST);
if (sv->sym->type.t & VT_STATIC) { // XXX do this per linker relax
greloca(cur_text_section, sv->sym, ind,
R_RISCV_PCREL_HI20, sv->c.i);
sv->c.i = 0;
} else {
if (((unsigned)fc + (1 << 11)) >> 12)
tcc_error("unimp: large addend for global address (0x%llx)", sv->c.i);
greloca(cur_text_section, sv->sym, ind,
R_RISCV_GOT_HI20, 0);
doload = 1;
}
if (!label.v) {
label.v = tok_alloc(".L0 ", 4)->tok;
label.type.t = VT_VOID | VT_STATIC;
}
label.c = 0; /* force new local ELF symbol */
put_extern_sym(&label, cur_text_section, ind, 0);
rr = is_ireg(r) ? ireg(r) : 5;
o(0x17 | (rr << 7)); // auipc RR, 0 %pcrel_hi(sym)+addend
greloca(cur_text_section, &label, ind,
doload || !forstore
? R_RISCV_PCREL_LO12_I : R_RISCV_PCREL_LO12_S, 0);
if (doload) {
EI(0x03, 3, rr, rr, 0); // ld RR, 0(RR)
}
} else if (v == VT_LOCAL || v == VT_LLOCAL) {
rr = 8; // s0
if (fc != sv->c.i)
tcc_error("unimp: store(giant local off) (0x%llx)", (long long)sv->c.i);
if (((unsigned)fc + (1 << 11)) >> 12) {
rr = is_ireg(r) ? ireg(r) : 5; // t0
o(0x37 | (rr << 7) | ((0x800 + fc) & 0xfffff000)); //lui RR, upper(fc)
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 0, rr, rr, 8, 0); // add RR, RR, s0
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
sv->c.i = fc << 20 >> 20;
}
} else
tcc_error("uhh");
return rr;
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
ST_FUNC void load(int r, SValue *sv)
{
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
int fr = sv->r;
int v = fr & VT_VALMASK;
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
int rr = is_ireg(r) ? ireg(r) : freg(r);
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
int fc = sv->c.i;
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
int bt = sv->type.t & VT_BTYPE;
int align, size = type_size(&sv->type, &align);
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
if (fr & VT_LVAL) {
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
int func3, opcode = is_freg(r) ? 0x07 : 0x03, br;
assert (!is_freg(r) || bt == VT_FLOAT || bt == VT_DOUBLE);
if (bt == VT_FUNC) /* XXX should be done in generic code */
size = PTR_SIZE;
func3 = size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3;
if (size < 4 && !is_float(sv->type.t) && (sv->type.t & VT_UNSIGNED))
func3 |= 4;
if (v == VT_LOCAL || (fr & VT_SYM)) {
br = load_symofs(r, sv, 0);
fc = sv->c.i;
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
} else if (v < VT_CONST) {
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
br = ireg(v);
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
/*if (((unsigned)fc + (1 << 11)) >> 12)
tcc_error("unimp: load(large addend) (0x%x)", fc);*/
fc = 0; // XXX store ofs in LVAL(reg)
} else if (v == VT_LLOCAL) {
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
br = load_symofs(r, sv, 0);
fc = sv->c.i;
EI(0x03, 3, rr, br, fc); // ld RR, fc(BR)
br = rr;
fc = 0;
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
} else {
tcc_error("unimp: load(non-local lval)");
}
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
EI(opcode, func3, rr, br, fc); // l[bhwd][u] / fl[wd] RR, fc(BR)
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
} else if (v == VT_CONST) {
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
int rb = 0, do32bit = 8, zext = 0;
riscv: Fix 73_arm.c some constants were loaded wrong (e.g. 0xffffabcdU), and risc-v needs to do explicit zero-extensions for widening from 32bit (not sign-extensions like the other 64bit targets). This makes the whole tests2.all testsuite work. Parameter passing is still not psABI-compliant, but internally consistent. (e.g. structs of two floats/doubles are passed in integer registers, but should sit in float regs).
2019-07-21 06:39:35 +03:00
assert((!is_float(sv->type.t) && is_ireg(r)) || bt == VT_LDOUBLE);
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
if (fr & VT_SYM) {
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
rb = load_symofs(r, sv, 0);
fc = sv->c.i;
riscv: fix 72_long_long_constant 32bit signed constants larger than 0x7ffff800 were handled wrongly.
2019-07-15 20:22:51 +03:00
do32bit = 0;
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
}
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
if (is_float(sv->type.t) && bt != VT_LDOUBLE)
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
tcc_error("unimp: load(float)");
riscv: Make 32_leds work * more ops: umod and udiv * large immediates: suboptimal code, e.g. when loading 0xffffffffU (which is what a cast from long to int does). tests2 work up to 67_macro_concat.
2019-07-14 04:26:38 +03:00
if (fc != sv->c.i) {
int64_t si = sv->c.i;
uint32_t pi;
si >>= 32;
riscv: load 64bit constants, and 32bit shifts fixes 95_bitfields. loading 64bit constants is suboptimal right now. int32_t shifts really need to use the W form, otherwise 'x << 24 >> 24' doesn't extract the low 8 bits.
2019-07-15 21:59:28 +03:00
if (si != 0) {
pi = si;
if (fc < 0)
pi++;
o(0x37 | (rr << 7) | (((pi + 0x800) & 0xfffff000))); // lui RR, up(up(fc))
EI(0x13, 0, rr, rr, (int)pi << 20 >> 20); // addi RR, RR, lo(up(fc))
EI(0x13, 1, rr, rr, 12); // slli RR, RR, 12
EI(0x13, 0, rr, rr, (fc + (1 << 19)) >> 20); // addi RR, RR, up(lo(fc))
EI(0x13, 1, rr, rr, 12); // slli RR, RR, 12
fc = fc << 12 >> 12;
EI(0x13, 0, rr, rr, fc >> 8); // addi RR, RR, lo1(lo(fc))
EI(0x13, 1, rr, rr, 8); // slli RR, RR, 8
fc &= 0xff;
rb = rr;
do32bit = 0;
riscv: Fix 73_arm.c some constants were loaded wrong (e.g. 0xffffabcdU), and risc-v needs to do explicit zero-extensions for widening from 32bit (not sign-extensions like the other 64bit targets). This makes the whole tests2.all testsuite work. Parameter passing is still not psABI-compliant, but internally consistent. (e.g. structs of two floats/doubles are passed in integer registers, but should sit in float regs).
2019-07-21 06:39:35 +03:00
} else if (bt == VT_LLONG) {
/* A 32bit unsigned constant for a 64bit type.
lui always sign extends, so we need to do an explicit zext.*/
zext = 1;
riscv: load 64bit constants, and 32bit shifts fixes 95_bitfields. loading 64bit constants is suboptimal right now. int32_t shifts really need to use the W form, otherwise 'x << 24 >> 24' doesn't extract the low 8 bits.
2019-07-15 21:59:28 +03:00
}
riscv: Make 32_leds work * more ops: umod and udiv * large immediates: suboptimal code, e.g. when loading 0xffffffffU (which is what a cast from long to int does). tests2 work up to 67_macro_concat.
2019-07-14 04:26:38 +03:00
}
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
if (((unsigned)fc + (1 << 11)) >> 12)
o(0x37 | (rr << 7) | ((0x800 + fc) & 0xfffff000)), rb = rr; //lui RR, upper(fc)
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
if (fc || (rr != rb) || do32bit || (fr & VT_SYM))
riscv: GOT loads, signed remainder, ELF flags * support loading sym addresses from GOT: important for weak syms, fixes 104_inline. This is still incomplete, it only works for taking the sym address, not for directly loading/storing into such symbols (i.e. not for VT_LVAL) * another op: '%' * ELF flags: add EF_RISCV_FLOAT_ABI_DOUBLE, which is our ABI.
2019-07-16 00:15:51 +03:00
EI(0x13 | do32bit, 0, rr, rb, fc << 20 >> 20); // addi[w] R, x0|R, FC
riscv: Fix 73_arm.c some constants were loaded wrong (e.g. 0xffffabcdU), and risc-v needs to do explicit zero-extensions for widening from 32bit (not sign-extensions like the other 64bit targets). This makes the whole tests2.all testsuite work. Parameter passing is still not psABI-compliant, but internally consistent. (e.g. structs of two floats/doubles are passed in integer registers, but should sit in float regs).
2019-07-21 06:39:35 +03:00
if (zext) {
EI(0x13, 1, rr, rr, 32); // slli RR, RR, 32
EI(0x13, 5, rr, rr, 32); // srli RR, RR, 32
}
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
} else if (v == VT_LOCAL) {
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
int br = load_symofs(r, sv, 0);
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
assert(is_ireg(r));
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
fc = sv->c.i;
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
EI(0x13, 0, rr, br, fc); // addi R, s0, FC
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
} else if (v < VT_CONST) { /* reg-reg */
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
//assert(!fc); XXX support offseted regs
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
if (is_freg(r) && is_freg(v))
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x53, 0, rr, freg(v), freg(v), bt == VT_DOUBLE ? 0x11 : 0x10); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
else if (is_ireg(r) && is_ireg(v))
EI(0x13, 0, rr, ireg(v), 0); // addi RR, V, 0 == mv RR, V
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
else {
int func7 = is_ireg(r) ? 0x70 : 0x78;
if (size == 8)
func7 |= 1;
assert(size == 4 || size == 8);
o(0x53 | (rr << 7) | ((is_freg(v) ? freg(v) : ireg(v)) << 15)
| (func7 << 25)); // fmv.{w.x, x.w, d.x, x.d} RR, VR
}
riscv: Optimize compares don't convert to 1/0 prematurely, we can save enough info in the VT_CMP metadata to be usable for the gtst branch expansion.
2019-08-14 18:40:34 +03:00
} else if (v == VT_CMP) {
int op = vtop->cmp_op;
int a = vtop->cmp_r & 0xff;
int b = (vtop->cmp_r >> 8) & 0xff;
int inv = 0;
switch (op) {
case TOK_ULT:
case TOK_UGE:
case TOK_ULE:
case TOK_UGT:
case TOK_LT:
case TOK_GE:
case TOK_LE:
case TOK_GT:
if (op & 1) { // remove [U]GE,GT
inv = 1;
op--;
}
if ((op & 7) == 6) { // [U]LE
int t = a; a = b; b = t;
inv ^= 1;
}
ER(0x33, (op > TOK_UGT) ? 2 : 3, rr, a, b, 0); // slt[u] d, a, b
if (inv)
EI(0x13, 4, rr, rr, 1); // xori d, d, 1
break;
case TOK_NE:
case TOK_EQ:
if (rr != a || b)
ER(0x33, 0, rr, a, b, 0x20); // sub d, a, b
if (op == TOK_NE)
ER(0x33, 3, rr, 0, rr, 0); // sltu d, x0, d == snez d,d
else
EI(0x13, 3, rr, rr, 1); // sltiu d, d, 1 == seqz d,d
break;
}
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
} else if ((v & ~1) == VT_JMP) {
int t = v & 1;
assert(is_ireg(r));
EI(0x13, 0, rr, 0, t); // addi RR, x0, t
gjmp_addr(ind + 8);
gsym(fc);
EI(0x13, 0, rr, 0, t ^ 1); // addi RR, x0, !t
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
} else
tcc_error("unimp: load(non-const)");
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
ST_FUNC void store(int r, SValue *sv)
{
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
int fr = sv->r & VT_VALMASK;
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
int rr = is_ireg(r) ? ireg(r) : freg(r), ptrreg;
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
int fc = sv->c.i;
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
int bt = sv->type.t & VT_BTYPE;
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
int align, size = type_size(&sv->type, &align);
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
assert(!is_float(bt) || is_freg(r) || bt == VT_LDOUBLE);
/* long doubles are in two integer registers, but the load/store
primitives only deal with one, so do as if it's one reg. */
if (bt == VT_LDOUBLE)
size = align = 8;
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
if (bt == VT_STRUCT)
tcc_error("unimp: store(struct)");
if (size > 8)
tcc_error("unimp: large sized store");
assert(sv->r & VT_LVAL);
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
if (fr == VT_LOCAL || (sv->r & VT_SYM)) {
ptrreg = load_symofs(-1, sv, 1);
fc = sv->c.i;
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
} else if (fr < VT_CONST) {
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
ptrreg = ireg(fr);
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
/*if (((unsigned)fc + (1 << 11)) >> 12)
tcc_error("unimp: store(large addend) (0x%x)", fc);*/
fc = 0; // XXX support offsets regs
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
} else
tcc_error("implement me: %s(!local)", __FUNCTION__);
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
ES(is_freg(r) ? 0x27 : 0x23, // fs... | s...
size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3, // ... [wd] | [bhwd]
ptrreg, rr, fc); // RR, fc(base)
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
static void gcall_or_jmp(int docall)
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
{
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
int tr = docall ? 1 : 5; // ra or t0
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST &&
((vtop->r & VT_SYM) && vtop->c.i == (int)vtop->c.i)) {
/* constant symbolic case -> simple relocation */
greloca(cur_text_section, vtop->sym, ind,
R_RISCV_CALL_PLT, (int)vtop->c.i);
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
o(0x17 | (tr << 7)); // auipc TR, 0 %call(func)
EI(0x67, 0, tr, tr, 0);// jalr TR, r(TR)
riscv: fix 90_struct-init indirect calls were broken.
2019-07-16 00:36:36 +03:00
} else if (vtop->r < VT_CONST) {
int r = ireg(vtop->r);
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
EI(0x67, 0, tr, r, 0); // jalr TR, 0(R)
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
} else {
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
int r = TREG_RA;
load(r, vtop);
r = ireg(r);
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
EI(0x67, 0, tr, r, 0); // jalr TR, 0(R)
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
}
}
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
static void reg_pass_rec(CType *type, int *rc, int *fieldofs, int ofs)
riscv: Start fixing float struct passing/returnig this fixes ret_2float_test, ret_2double_test and ret_8plus2double_test of abitest.c. The common gfunc_return actually works for these cases, so let's use that for now. The ret_mixed_test (as well as mixed2 and mixed3) are left broken, and tccgen.c:gfunc_return can't be used for that as is, so I'll leave the gfunc_return implementation in riscv64-gen.c for now, I'll have to think about this some more.
2019-07-23 00:09:05 +03:00
{
if ((type->t & VT_BTYPE) == VT_STRUCT) {
Sym *f;
if (type->ref->type.t == VT_UNION)
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
rc[0] = -1;
else for (f = type->ref->next; f; f = f->next)
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
reg_pass_rec(&f->type, rc, fieldofs, ofs + f->c);
riscv: Start fixing float struct passing/returnig this fixes ret_2float_test, ret_2double_test and ret_8plus2double_test of abitest.c. The common gfunc_return actually works for these cases, so let's use that for now. The ret_mixed_test (as well as mixed2 and mixed3) are left broken, and tccgen.c:gfunc_return can't be used for that as is, so I'll leave the gfunc_return implementation in riscv64-gen.c for now, I'll have to think about this some more.
2019-07-23 00:09:05 +03:00
} else if (type->t & VT_ARRAY) {
if (type->ref->c < 0 || type->ref->c > 2)
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
rc[0] = -1;
else {
int a, sz = type_size(&type->ref->type, &a);
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
reg_pass_rec(&type->ref->type, rc, fieldofs, ofs);
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
if (rc[0] > 2 || (rc[0] == 2 && type->ref->c > 1))
rc[0] = -1;
else if (type->ref->c == 2 && rc[0] && rc[1] == RC_FLOAT) {
rc[++rc[0]] = RC_FLOAT;
fieldofs[rc[0]] = ((ofs + sz) << 4)
| (type->ref->type.t & VT_BTYPE);
} else if (type->ref->c == 2)
rc[0] = -1;
}
} else if (rc[0] == 2 || rc[0] < 0 || (type->t & VT_BTYPE) == VT_LDOUBLE)
rc[0] = -1;
else if (!rc[0] || rc[1] == RC_FLOAT || is_float(type->t)) {
rc[++rc[0]] = is_float(type->t) ? RC_FLOAT : RC_INT;
fieldofs[rc[0]] = (ofs << 4) | (type->t & VT_BTYPE);
} else
rc[0] = -1;
riscv: Start fixing float struct passing/returnig this fixes ret_2float_test, ret_2double_test and ret_8plus2double_test of abitest.c. The common gfunc_return actually works for these cases, so let's use that for now. The ret_mixed_test (as well as mixed2 and mixed3) are left broken, and tccgen.c:gfunc_return can't be used for that as is, so I'll leave the gfunc_return implementation in riscv64-gen.c for now, I'll have to think about this some more.
2019-07-23 00:09:05 +03:00
}
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
static void reg_pass(CType *type, int *prc, int *fieldofs, int named)
{
prc[0] = 0;
reg_pass_rec(type, prc, fieldofs, 0);
if (prc[0] <= 0 || !named) {
int align, size = type_size(type, &align);
prc[0] = (size + 7) >> 3;
prc[1] = prc[2] = RC_INT;
fieldofs[1] = (0 << 4) | (size <= 1 ? VT_BYTE : size <= 2 ? VT_SHORT : size <= 4 ? VT_INT : VT_LLONG);
fieldofs[2] = (8 << 4) | (size <= 9 ? VT_BYTE : size <= 10 ? VT_SHORT : size <= 12 ? VT_INT : VT_LLONG);
}
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
ST_FUNC void gfunc_call(int nb_args)
{
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
int i, align, size, areg[2];
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
int info[nb_args ? nb_args : 1];
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
int stack_adj = 0, tempspace = 0, ofs, splitofs = 0;
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
SValue *sv;
Sym *sa;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
areg[0] = 0; /* int arg regs */
areg[1] = 8; /* float arg regs */
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
sa = vtop[-nb_args].type.ref->next;
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
for (i = 0; i < nb_args; i++) {
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
int nregs, byref = 0, tempofs;
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
int prc[3], fieldofs[3];
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
sv = &vtop[1 + i - nb_args];
sv->type.t &= ~VT_ARRAY; // XXX this should be done in tccgen.c
size = type_size(&sv->type, &align);
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
if (size > 16) {
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
if (align < XLEN)
align = XLEN;
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
tempspace = (tempspace + align - 1) & -align;
tempofs = tempspace;
tempspace += size;
size = align = 8;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
byref = 64 | (tempofs << 7);
riscv: Start fixing float struct passing/returnig this fixes ret_2float_test, ret_2double_test and ret_8plus2double_test of abitest.c. The common gfunc_return actually works for these cases, so let's use that for now. The ret_mixed_test (as well as mixed2 and mixed3) are left broken, and tccgen.c:gfunc_return can't be used for that as is, so I'll leave the gfunc_return implementation in riscv64-gen.c for now, I'll have to think about this some more.
2019-07-23 00:09:05 +03:00
}
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
reg_pass(&sv->type, prc, fieldofs, sa != 0);
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
if (!sa && align == 2*XLEN && size <= 2*XLEN)
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
areg[0] = (areg[0] + 1) & ~1;
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
nregs = prc[0];
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
if ((prc[1] == RC_INT && areg[0] >= 8)
|| (prc[1] == RC_FLOAT && areg[1] >= 16)
|| (nregs == 2 && prc[1] == RC_FLOAT && prc[2] == RC_FLOAT
&& areg[1] >= 15)
|| (nregs == 2 && prc[1] != prc[2]
&& (areg[1] >= 16 || areg[0] >= 8))) {
riscv: some long double support long double on risc-v is 128bit, but there are no registers for that type (without the Q ISA extension). They are passed like two 64bit integers values (with an exception for varargs, where it's an aligned register pair). This all requires some hacks in generic code as otherwise RC_FLOAT regs are tried for holding values of long double type, but we need a RC_INT register pair. This really could all use some cleanup for all archs. This doesn't implement any conversions of operations for long double, but it's enough to get 70_floating_point_literals working.
2019-07-14 06:48:15 +03:00
info[i] = 32;
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
if (align < XLEN)
align = XLEN;
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
stack_adj += (size + align - 1) & -align;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
if (!sa) /* one vararg on stack forces the rest on stack */
areg[0] = 8, areg[1] = 16;
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
} else {
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
info[i] = areg[prc[1] - 1]++;
if (!byref)
info[i] |= (fieldofs[1] & VT_BTYPE) << 12;
assert(!(fieldofs[1] >> 4));
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
if (nregs == 2) {
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
if (prc[2] == RC_FLOAT || areg[0] < 8)
info[i] |= (1 + areg[prc[2] - 1]++) << 7;
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
else {
info[i] |= 16;
stack_adj += 8;
}
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
if (!byref) {
assert((fieldofs[2] >> 4) < 2048);
riscv: factor load/store code split out common code and tidy result.
2019-08-13 04:19:53 +03:00
info[i] |= fieldofs[2] << (12 + 4); // includes offset
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
}
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
}
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
}
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
info[i] |= byref;
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
if (sa)
sa = sa->next;
}
stack_adj = (stack_adj + 15) & -16;
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
tempspace = (tempspace + 15) & -16;
if (stack_adj + tempspace) {
EI(0x13, 0, 2, 2, -(stack_adj + tempspace)); // addi sp, sp, -adj
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
for (i = ofs = 0; i < nb_args; i++) {
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
if (info[i] & (64 | 32)) {
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
vrotb(nb_args - i);
size = type_size(&vtop->type, &align);
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
if (info[i] & 64) {
vset(&char_pointer_type, TREG_SP, 0);
vpushi(stack_adj + (info[i] >> 7));
gen_op('+');
vpushv(vtop); // this replaces the old argument
vrott(3);
indir();
vtop->type = vtop[-1].type;
vswap();
vstore();
vpop();
size = align = 8;
}
if (info[i] & 32) {
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
if (align < XLEN)
align = XLEN;
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
/* Once we support offseted regs we can do this:
vset(&vtop->type, TREG_SP | VT_LVAL, ofs);
to construct the lvalue for the outgoing stack slot,
until then we have to jump through hoops. */
vset(&char_pointer_type, TREG_SP, 0);
ofs = (ofs + align - 1) & -align;
vpushi(ofs);
gen_op('+');
indir();
vtop->type = vtop[-1].type;
vswap();
vstore();
vtop->r = vtop->r2 = VT_CONST; // this arg is done
ofs += size;
}
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
vrott(nb_args - i);
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
} else if (info[i] & 16) {
assert(!splitofs);
splitofs = ofs;
ofs += 8;
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
}
}
}
for (i = 0; i < nb_args; i++) {
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
int ii = info[nb_args - 1 - i], r = ii, r2 = r;
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
if (!(r & 32)) {
CType origtype;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
int loadt;
riscv: some long double support long double on risc-v is 128bit, but there are no registers for that type (without the Q ISA extension). They are passed like two 64bit integers values (with an exception for varargs, where it's an aligned register pair). This all requires some hacks in generic code as otherwise RC_FLOAT regs are tried for holding values of long double type, but we need a RC_INT register pair. This really could all use some cleanup for all archs. This doesn't implement any conversions of operations for long double, but it's enough to get 70_floating_point_literals working.
2019-07-14 06:48:15 +03:00
r &= 15;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
r2 = r2 & 64 ? 0 : (r2 >> 7) & 31;
assert(r2 <= 16);
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
vrotb(i+1);
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
origtype = vtop->type;
size = type_size(&vtop->type, &align);
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
loadt = vtop->type.t & VT_BTYPE;
if (loadt == VT_STRUCT) {
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
loadt = (ii >> 12) & VT_BTYPE;
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
}
if (info[nb_args - 1 - i] & 16) {
assert(!r2);
r2 = 1 + TREG_RA;
}
if (loadt == VT_LDOUBLE) {
assert(r2);
r2--;
} else if (r2) {
test_lvalue();
vpushv(vtop);
}
riscv64: adjust for cast changes gfunc_call plays with types and needs to retain the unsignedness now (this was a latent problem before commit 35475b5).
2019-12-17 02:48:57 +03:00
vtop->type.t = loadt | (vtop->type.t & VT_UNSIGNED);
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
gv(r < 8 ? RC_R(r) : RC_F(r - 8));
vtop->type = origtype;
if (r2 && loadt != VT_LDOUBLE) {
r2--;
assert(r2 < 16 || r2 == TREG_RA);
vswap();
gaddrof();
vtop->type = char_pointer_type;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
vpushi(ii >> 20);
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
gen_op('+');
indir();
vtop->type = origtype;
loadt = vtop->type.t & VT_BTYPE;
riscv: Start fixing float struct passing/returnig this fixes ret_2float_test, ret_2double_test and ret_8plus2double_test of abitest.c. The common gfunc_return actually works for these cases, so let's use that for now. The ret_mixed_test (as well as mixed2 and mixed3) are left broken, and tccgen.c:gfunc_return can't be used for that as is, so I'll leave the gfunc_return implementation in riscv64-gen.c for now, I'll have to think about this some more.
2019-07-23 00:09:05 +03:00
if (loadt == VT_STRUCT) {
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
loadt = (ii >> 16) & VT_BTYPE;
riscv: Start fixing float struct passing/returnig this fixes ret_2float_test, ret_2double_test and ret_8plus2double_test of abitest.c. The common gfunc_return actually works for these cases, so let's use that for now. The ret_mixed_test (as well as mixed2 and mixed3) are left broken, and tccgen.c:gfunc_return can't be used for that as is, so I'll leave the gfunc_return implementation in riscv64-gen.c for now, I'll have to think about this some more.
2019-07-23 00:09:05 +03:00
}
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
save_reg_upstack(r2, 1);
riscv64: adjust for cast changes gfunc_call plays with types and needs to retain the unsignedness now (this was a latent problem before commit 35475b5).
2019-12-17 02:48:57 +03:00
vtop->type.t = loadt | (vtop->type.t & VT_UNSIGNED);
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
load(r2, vtop);
assert(r2 < VT_CONST);
riscv: Start fixing float struct passing/returnig this fixes ret_2float_test, ret_2double_test and ret_8plus2double_test of abitest.c. The common gfunc_return actually works for these cases, so let's use that for now. The ret_mixed_test (as well as mixed2 and mixed3) are left broken, and tccgen.c:gfunc_return can't be used for that as is, so I'll leave the gfunc_return implementation in riscv64-gen.c for now, I'll have to think about this some more.
2019-07-23 00:09:05 +03:00
vtop--;
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
vtop->r2 = r2;
riscv: some long double support long double on risc-v is 128bit, but there are no registers for that type (without the Q ISA extension). They are passed like two 64bit integers values (with an exception for varargs, where it's an aligned register pair). This all requires some hacks in generic code as otherwise RC_FLOAT regs are tried for holding values of long double type, but we need a RC_INT register pair. This really could all use some cleanup for all archs. This doesn't implement any conversions of operations for long double, but it's enough to get 70_floating_point_literals working.
2019-07-14 06:48:15 +03:00
}
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
if (info[nb_args - 1 - i] & 16) {
ES(0x23, 3, 2, ireg(vtop->r2), splitofs); // sd t0, ofs(sp)
vtop->r2 = VT_CONST;
} else if (loadt == VT_LDOUBLE && vtop->r2 != r2) {
assert(vtop->r2 <= 7 && r2 <= 7);
/* XXX we'd like to have 'gv' move directly into
the right class instead of us fixing it up. */
EI(0x13, 0, ireg(r2), ireg(vtop->r2), 0); // mv Ra+1, RR2
vtop->r2 = r2;
riscv: Start fixing float struct passing/returnig this fixes ret_2float_test, ret_2double_test and ret_8plus2double_test of abitest.c. The common gfunc_return actually works for these cases, so let's use that for now. The ret_mixed_test (as well as mixed2 and mixed3) are left broken, and tccgen.c:gfunc_return can't be used for that as is, so I'll leave the gfunc_return implementation in riscv64-gen.c for now, I'll have to think about this some more.
2019-07-23 00:09:05 +03:00
}
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
vrott(i+1);
}
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
}
vrotb(nb_args + 1);
riscv: Fix tcctest.c this is it! With this tcctest.c works, as well as compiling TCC with itself. abitest.c doesn't yet work due to known problems, all the rest does. There are still warnings during linking.
2019-07-22 07:46:37 +03:00
save_regs(nb_args + 1);
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
gcall_or_jmp(1);
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
vtop -= nb_args + 1;
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
if (stack_adj + tempspace)
EI(0x13, 0, 2, 2, stack_adj + tempspace); // addi sp, sp, adj
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
riscv: Fix stdarg_many_test if named params are passed on stack, the va_arg area begins after that, not at sp+0. Fixes abitest:stdarg_many_test.
2019-07-22 21:37:42 +03:00
static int func_sub_sp_offset, num_va_regs, func_va_list_ofs;
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
Fix bounds checking for linux/windows
2019-12-10 10:07:25 +03:00
ST_FUNC void gfunc_prolog(Sym *func_sym)
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
{
Fix bounds checking for linux/windows
2019-12-10 10:07:25 +03:00
CType *func_type = &func_sym->type;
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
int i, addr, align, size;
int param_addr = 0;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
int areg[2];
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
Sym *sym;
CType *type;
sym = func_type->ref;
riscv: Implement some loads and calls so that a hello world works.
2019-06-23 09:17:05 +03:00
loc = -16; // for ra and s0
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
func_sub_sp_offset = ind;
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
ind += 5 * 4;
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
areg[0] = 0, areg[1] = 0;
addr = 0;
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
/* if the function returns by reference, then add an
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
implicit pointer parameter */
size = type_size(&func_vt, &align);
if (size > 2 * XLEN) {
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
loc -= 8;
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
func_vc = loc;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
ES(0x23, 3, 8, 10 + areg[0]++, loc); // sd a0, loc(s0)
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
}
/* define parameters */
while ((sym = sym->next) != NULL) {
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
int byref = 0;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
int regcount;
int prc[3], fieldofs[3];
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
type = &sym->type;
size = type_size(type, &align);
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
if (size > 2 * XLEN) {
type = &char_pointer_type;
size = align = byref = 8;
}
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
reg_pass(type, prc, fieldofs, 1);
regcount = prc[0];
if (areg[prc[1] - 1] >= 8
|| (regcount == 2
&& ((prc[1] == RC_FLOAT && prc[2] == RC_FLOAT && areg[1] >= 7)
|| (prc[1] != prc[2] && (areg[1] >= 8 || areg[0] >= 8))))) {
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
if (align < XLEN)
align = XLEN;
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
addr = (addr + align - 1) & -align;
param_addr = addr;
addr += size;
} else {
riscv: fp parameters makes 23_type_coercion work. (clean up to 31_args)
2019-07-14 02:37:02 +03:00
loc -= regcount * 8; // XXX could reserve only 'size' bytes
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
param_addr = loc;
for (i = 0; i < regcount; i++) {
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
if (areg[prc[1+i] - 1] >= 8) {
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
assert(i == 1 && regcount == 2 && !(addr & 7));
EI(0x03, 3, 5, 8, addr); // ld t0, addr(s0)
addr += 8;
ES(0x23, 3, 8, 5, loc + i*8); // sd t0, loc(s0)
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
} else if (prc[1+i] == RC_FLOAT) {
ES(0x27, (size / regcount) == 4 ? 2 : 3, 8, 10 + areg[1]++, loc + (fieldofs[i+1] >> 4)); // fs[wd] FAi, loc(s0)
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
} else {
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
ES(0x23, 3, 8, 10 + areg[0]++, loc + i*8); // sd aX, loc(s0) // XXX
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
}
}
}
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
sym_push(sym->v & ~SYM_FIELD, &sym->type,
remove VT_LVAL_BYTE etc. For some reason there was no point for that anymore.
2019-12-16 20:48:31 +03:00
(byref ? VT_LLOCAL : VT_LOCAL) | VT_LVAL,
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
param_addr);
}
riscv: Fix stdarg_many_test if named params are passed on stack, the va_arg area begins after that, not at sp+0. Fixes abitest:stdarg_many_test.
2019-07-22 21:37:42 +03:00
func_va_list_ofs = addr;
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
num_va_regs = 0;
tccgen.c: cleanup debug support from 3e731e3a78c0b1f9a299afee2665b11d3c4c25fe tccgen.c: - make 'struct default_debug' const - pass TCCState* as parameter to tcc_debug_xxx functions - always check tcc_state->do_debug before calling functions - factor out tcc_debug_extern_sym() - remove formats "%lld"/"%llu" (not reliable on windows) xxx-gen files: - set func_vt/var from caller
2020-05-05 15:47:00 +03:00
if (func_var) {
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
for (; areg[0] < 8; areg[0]++) {
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
num_va_regs++;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
ES(0x23, 3, 8, 10 + areg[0], -8 + num_va_regs * 8); // sd aX, loc(s0)
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret,
int *ret_align, int *regsize)
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
{
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
int align, size = type_size(vt, &align), nregs;
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
int prc[3], fieldofs[3];
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
*ret_align = 1;
*regsize = 8;
if (size > 16)
return 0;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
reg_pass(vt, prc, fieldofs, 1);
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
nregs = prc[0];
if (nregs == 2 && prc[1] != prc[2])
return -1; /* generic code can't deal with this case */
if (prc[1] == RC_FLOAT) {
*regsize = size / nregs;
}
ret->t = fieldofs[1] & VT_BTYPE;
return nregs;
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
ST_FUNC void arch_transfer_ret_regs(int aftercall)
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
{
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
int prc[3], fieldofs[3];
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
reg_pass(&vtop->type, prc, fieldofs, 1);
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
assert(prc[0] == 2 && prc[1] != prc[2] && !(fieldofs[1] >> 4));
assert(vtop->r == (VT_LOCAL | VT_LVAL));
vpushv(vtop);
vtop->type.t = fieldofs[1] & VT_BTYPE;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
(aftercall ? store : load)(prc[1] == RC_INT ? REG_IRET : REG_FRET, vtop);
riscv: rewrite parameter passing this fixes the ret_mixed_test of abitest.c, now everything of the testsuite works. The generic code for returns is good enough for our use, except in the specific case of a mixed int/float structures returned in registers, so instead of duplicating the whole generic gfunc_return function, add another modus for gfunc_sret: returning -1 makes the actual register transfer by a new backend function.
2019-08-10 22:21:43 +03:00
vtop->c.i += fieldofs[2] >> 4;
vtop->type.t = fieldofs[2] & VT_BTYPE;
riscv: TLC of param passing factor and cleanup the param passing code somewhat.
2019-08-11 02:54:29 +03:00
(aftercall ? store : load)(prc[2] == RC_INT ? REG_IRET : REG_FRET, vtop);
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
vtop--;
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
ST_FUNC void gfunc_epilog(void)
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
{
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
int v, saved_ind, d, large_ofs_ind;
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
loc = (loc - num_va_regs * 8);
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
d = v = (-loc + 15) & -16;
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
if (v >= (1 << 11)) {
d = 16;
o(0x37 | (5 << 7) | ((0x800 + (v-16)) & 0xfffff000)); //lui t0, upper(v)
EI(0x13, 0, 5, 5, (v-16) << 20 >> 20); // addi t0, t0, lo(v)
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 0, 2, 2, 5, 0); // add sp, sp, t0
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
}
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
EI(0x03, 3, 1, 2, d - 8 - num_va_regs * 8); // ld ra, v-8(sp)
EI(0x03, 3, 8, 2, d - 16 - num_va_regs * 8); // ld s0, v-16(sp)
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
EI(0x13, 0, 2, 2, d); // addi sp, sp, v
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
EI(0x67, 0, 0, 1, 0); // jalr x0, 0(x1), aka ret
tccgen.c: cleanup reg classes wrap some copy&paste code into functions
2019-12-16 20:44:35 +03:00
large_ofs_ind = ind;
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
if (v >= (1 << 11)) {
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
EI(0x13, 0, 8, 2, d - num_va_regs * 8); // addi s0, sp, d
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
o(0x37 | (5 << 7) | ((0x800 + (v-16)) & 0xfffff000)); //lui t0, upper(v)
EI(0x13, 0, 5, 5, (v-16) << 20 >> 20); // addi t0, t0, lo(v)
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 0, 2, 2, 5, 0x20); // sub sp, sp, t0
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
gjmp_addr(func_sub_sp_offset + 5*4);
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
saved_ind = ind;
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
ind = func_sub_sp_offset;
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
EI(0x13, 0, 2, 2, -d); // addi sp, sp, -d
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
ES(0x23, 3, 2, 1, d - 8 - num_va_regs * 8); // sd ra, d-8(sp)
ES(0x23, 3, 2, 8, d - 16 - num_va_regs * 8); // sd s0, d-16(sp)
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
if (v < (1 << 11))
riscv: implement stdarg functions this also fixes passing of params > 16 bytes. In riscv they aren't passed by value on stack, but via reference (and because callees are allowed to modify by-ref params the caller must allocate an own copy per call). This fixes the stdarg parts of 73_arm.c.
2019-07-21 04:25:12 +03:00
EI(0x13, 0, 8, 2, d - num_va_regs * 8); // addi s0, sp, d
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
else
gjmp_addr(large_ofs_ind);
if ((ind - func_sub_sp_offset) != 5*4)
EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
ind = saved_ind;
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
ST_FUNC void gen_va_start(void)
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
{
riscv: Fix stdarg_many_test if named params are passed on stack, the va_arg area begins after that, not at sp+0. Fixes abitest:stdarg_many_test.
2019-07-22 21:37:42 +03:00
vtop--;
vset(&char_pointer_type, VT_LOCAL, func_va_list_ofs);
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
ST_FUNC void gen_fill_nops(int bytes)
{
if ((bytes & 3))
tcc_error("alignment of code section not multiple of 4");
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
while (bytes > 0) {
EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
bytes -= 4;
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
// Generate forward branch to label:
ST_FUNC int gjmp(int t)
{
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
if (nocode_wanted)
return t;
o(t);
return ind - 4;
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
// Generate branch to known address:
ST_FUNC void gjmp_addr(int a)
{
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
uint32_t r = a - ind, imm;
riscv: support large stack and far jumps for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).
2019-07-17 23:23:45 +03:00
if ((r + (1 << 21)) & ~((1U << 22) - 2)) {
o(0x17 | (5 << 7) | (((r + 0x800) & 0xfffff000))); // lui RR, up(r)
r = (int)r << 20 >> 20;
EI(0x67, 0, 0, 5, r); // jalr x0, r(t0)
} else {
imm = (((r >> 12) & 0xff) << 12)
| (((r >> 11) & 1) << 20)
| (((r >> 1) & 0x3ff) << 21)
| (((r >> 20) & 1) << 31);
o(0x6f | imm); // jal x0, imm == j imm
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
ST_FUNC int gjmp_cond(int op, int t)
{
riscv: Optimize compares don't convert to 1/0 prematurely, we can save enough info in the VT_CMP metadata to be usable for the gtst branch expansion.
2019-08-14 18:40:34 +03:00
int tmp;
int a = vtop->cmp_r & 0xff;
int b = (vtop->cmp_r >> 8) & 0xff;
switch (op) {
case TOK_ULT: op = 6; break;
case TOK_UGE: op = 7; break;
case TOK_ULE: op = 7; tmp = a; a = b; b = tmp; break;
case TOK_UGT: op = 6; tmp = a; a = b; b = tmp; break;
case TOK_LT: op = 4; break;
case TOK_GE: op = 5; break;
case TOK_LE: op = 5; tmp = a; a = b; b = tmp; break;
case TOK_GT: op = 4; tmp = a; a = b; b = tmp; break;
case TOK_NE: op = 1; break;
case TOK_EQ: op = 0; break;
}
o(0x63 | (op ^ 1) << 12 | a << 15 | b << 20 | 8 << 7); // bOP a,b,+4
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
return gjmp(t);
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
ST_FUNC int gjmp_append(int n, int t)
{
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
void *p;
/* insert jump list n into t */
if (n) {
uint32_t n1 = n, n2;
while ((n2 = read32le(p = cur_text_section->data + n1)))
n1 = n2;
write32le(p, t);
t = n;
}
return t;
}
static void gen_opil(int op, int ll)
{
int a, b, d;
riscv: Add special cases for const operands RISC-V supports small immediates for some operations, let's use them.
2019-08-13 04:21:58 +03:00
int func3 = 0;
ll = ll ? 0 : 8;
if ((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
int fc = vtop->c.i;
if (fc == vtop->c.i && !(((unsigned)fc + (1 << 11)) >> 12)) {
int cll = 0;
vswap();
gv(RC_INT);
a = ireg(vtop[0].r);
--vtop;
d = get_reg(RC_INT);
++vtop;
vswap();
switch (op) {
case '-':
if (fc <= -(1 << 11))
break;
fc = -fc;
case '+':
func3 = 0; // addi d, a, fc
do_cop:
EI(0x13 | cll, func3, ireg(d), a, fc);
--vtop;
riscv: Optimize compares don't convert to 1/0 prematurely, we can save enough info in the VT_CMP metadata to be usable for the gtst branch expansion.
2019-08-14 18:40:34 +03:00
if (op >= TOK_ULT && op <= TOK_GT) {
vset_VT_CMP(TOK_NE);
vtop->cmp_r = ireg(d) | 0 << 8;
} else
vtop[0].r = d;
riscv: Add special cases for const operands RISC-V supports small immediates for some operations, let's use them.
2019-08-13 04:21:58 +03:00
return;
case TOK_LE:
if (fc >= (1 << 11) - 1)
break;
++fc;
case TOK_LT: func3 = 2; goto do_cop; // slti d, a, fc
case TOK_ULE:
if (fc >= (1 << 11) - 1)
break;
++fc;
case TOK_ULT: func3 = 3; goto do_cop; // sltiu d, a, fc
case '^': func3 = 4; goto do_cop; // xori d, a, fc
case '|': func3 = 6; goto do_cop; // ori d, a, fc
case '&': func3 = 7; goto do_cop; // andi d, a, fc
case TOK_SHL: func3 = 1; fc &= 63; goto do_cop; // slli d, a, fc
case TOK_SHR: func3 = 5; cll = ll; fc &= 63; goto do_cop; // srli d, a, fc
case TOK_SAR: func3 = 5; cll = ll; fc = 1024 | (fc & 63); goto do_cop;
case TOK_UGE:
case TOK_UGT:
case TOK_GE:
case TOK_GT:
gen_opil(op - 1, ll);
riscv: Optimize compares don't convert to 1/0 prematurely, we can save enough info in the VT_CMP metadata to be usable for the gtst branch expansion.
2019-08-14 18:40:34 +03:00
vtop->cmp_op ^= 1;
riscv: Add special cases for const operands RISC-V supports small immediates for some operations, let's use them.
2019-08-13 04:21:58 +03:00
return;
case TOK_NE:
case TOK_EQ:
if (fc)
gen_opil('-', ll), a = ireg(vtop++->r);
--vtop;
riscv: Optimize compares don't convert to 1/0 prematurely, we can save enough info in the VT_CMP metadata to be usable for the gtst branch expansion.
2019-08-14 18:40:34 +03:00
vset_VT_CMP(op);
vtop->cmp_r = a | 0 << 8;
riscv: Add special cases for const operands RISC-V supports small immediates for some operations, let's use them.
2019-08-13 04:21:58 +03:00
return;
}
}
}
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
gv2(RC_INT, RC_INT);
a = ireg(vtop[-1].r);
b = ireg(vtop[0].r);
vtop -= 2;
d = get_reg(RC_INT);
vtop++;
vtop[0].r = d;
d = ireg(d);
switch (op) {
default:
riscv: Optimize compares don't convert to 1/0 prematurely, we can save enough info in the VT_CMP metadata to be usable for the gtst branch expansion.
2019-08-14 18:40:34 +03:00
if (op >= TOK_ULT && op <= TOK_GT) {
vset_VT_CMP(op);
vtop->cmp_r = a | b << 8;
break;
}
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
tcc_error("implement me: %s(%s)", __FUNCTION__, get_tok_str(op, NULL));
riscv: Optimize compares don't convert to 1/0 prematurely, we can save enough info in the VT_CMP metadata to be usable for the gtst branch expansion.
2019-08-14 18:40:34 +03:00
break;
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
case '+':
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 0, d, a, b, 0); // add d, a, b
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
break;
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
case '-':
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 0, d, a, b, 0x20); // sub d, a, b
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
break;
riscv: Add sar, shr insn fixes 92_enum_bitfield.
2019-07-15 20:34:08 +03:00
case TOK_SAR:
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33 | ll, 5, d, a, b, 0x20); // sra d, a, b
riscv: Add sar, shr insn fixes 92_enum_bitfield.
2019-07-15 20:34:08 +03:00
break;
case TOK_SHR:
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33 | ll, 5, d, a, b, 0); // srl d, a, b
riscv: Add sar, shr insn fixes 92_enum_bitfield.
2019-07-15 20:34:08 +03:00
break;
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
case TOK_SHL:
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 1, d, a, b, 0); // sll d, a, b
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
break;
case '*':
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 0, d, a, b, 1); // mul d, a, b
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
break;
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
case '/':
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 4, d, a, b, 1); // div d, a, b
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
break;
case '&':
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 7, d, a, b, 0); // and d, a, b
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
break;
case '^':
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 4, d, a, b, 0); // xor d, a, b
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
break;
case '|':
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 6, d, a, b, 0); // or d, a, b
riscv: More insns, operands and arg slots * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div
2019-07-14 01:26:38 +03:00
break;
riscv: GOT loads, signed remainder, ELF flags * support loading sym addresses from GOT: important for weak syms, fixes 104_inline. This is still incomplete, it only works for taking the sym address, not for directly loading/storing into such symbols (i.e. not for VT_LVAL) * another op: '%' * ELF flags: add EF_RISCV_FLOAT_ABI_DOUBLE, which is our ABI.
2019-07-16 00:15:51 +03:00
case '%':
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 6, d, a, b, 1); // rem d, a, b
riscv: GOT loads, signed remainder, ELF flags * support loading sym addresses from GOT: important for weak syms, fixes 104_inline. This is still incomplete, it only works for taking the sym address, not for directly loading/storing into such symbols (i.e. not for VT_LVAL) * another op: '%' * ELF flags: add EF_RISCV_FLOAT_ABI_DOUBLE, which is our ABI.
2019-07-16 00:15:51 +03:00
break;
riscv: Make 32_leds work * more ops: umod and udiv * large immediates: suboptimal code, e.g. when loading 0xffffffffU (which is what a cast from long to int does). tests2 work up to 67_macro_concat.
2019-07-14 04:26:38 +03:00
case TOK_UMOD:
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 7, d, a, b, 1); // remu d, a, b
riscv: Make 32_leds work * more ops: umod and udiv * large immediates: suboptimal code, e.g. when loading 0xffffffffU (which is what a cast from long to int does). tests2 work up to 67_macro_concat.
2019-07-14 04:26:38 +03:00
break;
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
case TOK_PDIV:
riscv: Make 32_leds work * more ops: umod and udiv * large immediates: suboptimal code, e.g. when loading 0xffffffffU (which is what a cast from long to int does). tests2 work up to 67_macro_concat.
2019-07-14 04:26:38 +03:00
case TOK_UDIV:
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 5, d, a, b, 1); // divu d, a, b
riscv: Make 32_leds work * more ops: umod and udiv * large immediates: suboptimal code, e.g. when loading 0xffffffffU (which is what a cast from long to int does). tests2 work up to 67_macro_concat.
2019-07-14 04:26:38 +03:00
break;
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
ST_FUNC void gen_opi(int op)
{
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
gen_opil(op, 0);
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
ST_FUNC void gen_opl(int op)
{
riscv: Add more ops and fixes * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.
2019-06-24 03:34:46 +03:00
gen_opil(op, 1);
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
ST_FUNC void gen_opf(int op)
{
riscv: float ops * compares * add/sub/mul/div * float-float converts makes 22_floating_point work.
2019-07-14 02:28:46 +03:00
int rs1, rs2, rd, dbl, invert;
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
if (vtop[0].type.t == VT_LDOUBLE) {
CType type = vtop[0].type;
int func = 0;
int cond = -1;
switch (op) {
case '*': func = TOK___multf3; break;
case '+': func = TOK___addtf3; break;
case '-': func = TOK___subtf3; break;
case '/': func = TOK___divtf3; break;
case TOK_EQ: func = TOK___eqtf2; cond = 1; break;
case TOK_NE: func = TOK___netf2; cond = 0; break;
case TOK_LT: func = TOK___lttf2; cond = 10; break;
case TOK_GE: func = TOK___getf2; cond = 11; break;
case TOK_LE: func = TOK___letf2; cond = 12; break;
case TOK_GT: func = TOK___gttf2; cond = 13; break;
default: assert(0); break;
}
vpush_global_sym(&func_old_type, func);
vrott(3);
gfunc_call(2);
vpushi(0);
vtop->r = REG_IRET;
vtop->r2 = cond < 0 ? TREG_R(1) : VT_CONST;
if (cond < 0)
vtop->type = type;
else {
vpushi(0);
gen_opil(op, 1);
}
return;
}
riscv: float ops * compares * add/sub/mul/div * float-float converts makes 22_floating_point work.
2019-07-14 02:28:46 +03:00
gv2(RC_FLOAT, RC_FLOAT);
assert(vtop->type.t == VT_DOUBLE || vtop->type.t == VT_FLOAT);
dbl = vtop->type.t == VT_DOUBLE;
rs1 = freg(vtop[-1].r);
rs2 = freg(vtop->r);
vtop--;
invert = 0;
switch(op) {
default:
assert(0);
case '+':
op = 0; // fadd
arithop:
rd = get_reg(RC_FLOAT);
vtop->r = rd;
rd = freg(rd);
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x53, 7, rd, rs1, rs2, dbl | (op << 2)); // fop.[sd] RD, RS1, RS2 (dyn rm)
riscv: float ops * compares * add/sub/mul/div * float-float converts makes 22_floating_point work.
2019-07-14 02:28:46 +03:00
break;
case '-':
op = 1; // fsub
goto arithop;
case '*':
op = 2; // fmul
goto arithop;
case '/':
op = 3; // fdiv
goto arithop;
case TOK_EQ:
op = 2; // EQ
cmpop:
rd = get_reg(RC_INT);
vtop->r = rd;
rd = ireg(rd);
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x53, op, rd, rs1, rs2, dbl | 0x50); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)
riscv: float ops * compares * add/sub/mul/div * float-float converts makes 22_floating_point work.
2019-07-14 02:28:46 +03:00
if (invert)
EI(0x13, 4, rd, rd, 1); // xori RD, 1
break;
case TOK_NE:
invert = 1;
op = 2; // EQ
goto cmpop;
case TOK_LT:
op = 1; // LT
goto cmpop;
case TOK_LE:
op = 0; // LE
goto cmpop;
case TOK_GT:
op = 1; // LT
rd = rs1, rs1 = rs2, rs2 = rd;
goto cmpop;
case TOK_GE:
op = 0; // LE
rd = rs1, rs1 = rs2, rs2 = rd;
goto cmpop;
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
ST_FUNC void gen_cvt_sxtw(void)
{
riscv: more insns * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.
2019-06-24 04:36:50 +03:00
/* XXX on risc-v the registers are usually sign-extended already.
Let's try to not do anything here. */
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
ST_FUNC void gen_cvt_itof(int t)
{
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
int rr = ireg(gv(RC_INT)), dr;
int u = vtop->type.t & VT_UNSIGNED;
int l = (vtop->type.t & VT_BTYPE) == VT_LLONG;
if (t == VT_LDOUBLE) {
int func = l ?
(u ? TOK___floatunditf : TOK___floatditf) :
(u ? TOK___floatunsitf : TOK___floatsitf);
vpush_global_sym(&func_old_type, func);
vrott(2);
gfunc_call(1);
vpushi(0);
vtop->type.t = t;
vtop->r = REG_IRET;
vtop->r2 = TREG_R(1);
} else {
vtop--;
dr = get_reg(RC_FLOAT);
vtop++;
vtop->r = dr;
dr = freg(dr);
EIu(0x53, 7, dr, rr, ((0x68 | (t == VT_DOUBLE ? 1 : 0)) << 5) | (u ? 1 : 0) | (l ? 2 : 0)); // fcvt.[sd].[wl][u]
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
ST_FUNC void gen_cvt_ftoi(int t)
{
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
int ft = vtop->type.t & VT_BTYPE;
int l = (t & VT_BTYPE) == VT_LLONG;
int u = t & VT_UNSIGNED;
if (ft == VT_LDOUBLE) {
int func = l ?
(u ? TOK___fixunstfdi : TOK___fixtfdi) :
(u ? TOK___fixunstfsi : TOK___fixtfsi);
vpush_global_sym(&func_old_type, func);
vrott(2);
gfunc_call(1);
vpushi(0);
vtop->type.t = t;
vtop->r = REG_IRET;
} else {
int rr = freg(gv(RC_FLOAT)), dr;
vtop--;
dr = get_reg(RC_INT);
vtop++;
vtop->r = dr;
dr = ireg(dr);
riscv: Fix ftoi and ftof(long double->float) float to int must be truncations, not normal rounding. And ftof was typoed to select the wrong conversion function. This fixes tcctest.c completely. (make -C tests test1)
2019-07-22 03:31:08 +03:00
EIu(0x53, 1, dr, rr, ((0x60 | (ft == VT_DOUBLE ? 1 : 0)) << 5) | (u ? 1 : 0) | (l ? 2 : 0)); // fcvt.[wl][u].[sd] rtz
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: float ops * compares * add/sub/mul/div * float-float converts makes 22_floating_point work.
2019-07-14 02:28:46 +03:00
ST_FUNC void gen_cvt_ftof(int dt)
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
{
riscv: float ops * compares * add/sub/mul/div * float-float converts makes 22_floating_point work.
2019-07-14 02:28:46 +03:00
int st = vtop->type.t & VT_BTYPE, rs, rd;
dt &= VT_BTYPE;
if (st == dt)
return;
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
if (dt == VT_LDOUBLE || st == VT_LDOUBLE) {
int func = (dt == VT_LDOUBLE) ?
(st == VT_FLOAT ? TOK___extendsftf2 : TOK___extenddftf2) :
riscv: Fix ftoi and ftof(long double->float) float to int must be truncations, not normal rounding. And ftof was typoed to select the wrong conversion function. This fixes tcctest.c completely. (make -C tests test1)
2019-07-22 03:31:08 +03:00
(dt == VT_FLOAT ? TOK___trunctfsf2 : TOK___trunctfdf2);
riscv: Fix tcctest.c this is it! With this tcctest.c works, as well as compiling TCC with itself. abitest.c doesn't yet work due to known problems, all the rest does. There are still warnings during linking.
2019-07-22 07:46:37 +03:00
/* We can't use gfunc_call, as func_old_type works like vararg
functions, and on riscv unnamed float args are passed like
integers. But we really need them in the float argument registers
for extendsftf2/extenddftf2. So, do it explicitely. */
save_regs(1);
if (dt == VT_LDOUBLE)
gv(RC_F(0));
else {
gv(RC_R(0));
assert(vtop->r2 < 7);
if (vtop->r2 != 1 + vtop->r) {
EI(0x13, 0, ireg(vtop->r) + 1, ireg(vtop->r2), 0); // mv Ra+1, RR2
vtop->r2 = 1 + vtop->r;
}
}
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
vpush_global_sym(&func_old_type, func);
riscv: Fix tcctest.c this is it! With this tcctest.c works, as well as compiling TCC with itself. abitest.c doesn't yet work due to known problems, all the rest does. There are still warnings during linking.
2019-07-22 07:46:37 +03:00
gcall_or_jmp(1);
vtop -= 2;
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
vpushi(0);
vtop->type.t = dt;
if (dt == VT_LDOUBLE)
vtop->r = REG_IRET, vtop->r2 = REG_IRET+1;
else
vtop->r = REG_FRET;
} else {
assert (dt == VT_FLOAT || dt == VT_DOUBLE);
assert (st == VT_FLOAT || st == VT_DOUBLE);
rs = gv(RC_FLOAT);
rd = get_reg(RC_FLOAT);
if (dt == VT_DOUBLE)
riscv64: fcvt.d.s doesn't need a rounding mode it doesn't round so the RM field can be zero. According to some sourcs it should be set to zero by software in these cases, and the binutils disassembler doesn't like us setting it to 7. This shouldn't matter in practice, but who knows.
2020-04-16 01:00:13 +03:00
EI(0x53, 0, freg(rd), freg(rs), 0x21 << 5); // fcvt.d.s RD, RS (no rm)
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
else
riscv64: fcvt.d.s doesn't need a rounding mode it doesn't round so the RM field can be zero. According to some sourcs it should be set to zero by software in these cases, and the binutils disassembler doesn't like us setting it to 7. This shouldn't matter in practice, but who knows.
2020-04-16 01:00:13 +03:00
EI(0x53, 7, freg(rd), freg(rs), (0x20 << 5) | 1); // fcvt.s.d RD, RS (dyn rm)
riscv: some work on large function arguments like long double (16 bytes) and structs. Not completely correct, but 73_arm64 somewhat works now (when the stdarg part is disabled), though with some errors. What's definitely incorrect is arguments of a mixed int/float struct. I'm using VT_LDOUBLE (which conveniently has to be placed in a int-reg-pair) to load/store structure arguments of size > 8 and <= 16, and that can lead to overreads.
2019-07-18 05:51:52 +03:00
vtop->r = rd;
}
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
ST_FUNC void ggoto(void)
{
riscv: Implement long double support for the implementation of operations we can reuse the ones from lib/lib-arm64.c, risc-v long double is also float128. Also implement ggoto, and PDIV, and use t0 in load/store as temporary register if necessary, not one given by get_reg (the latter can destroy assignments of long double parameters in function calls that are already set up). This let's us compile tcc.c and tcctest.c, though both don't yet work.
2019-07-22 02:23:27 +03:00
gcall_or_jmp(0);
vtop--;
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
riscv: hacky prolog, epilog and return this now allows to compile a simple working example: int main(void) { return 0; }
2019-06-23 06:19:37 +03:00
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
ST_FUNC void gen_vla_sp_save(int addr)
{
riscv: Implement VLA stuff makes 78_vla_label and 79_vla_continue work.
2019-07-15 22:42:29 +03:00
ES(0x23, 3, 8, 2, addr); // sd sp, fc(s0)
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
ST_FUNC void gen_vla_sp_restore(int addr)
{
riscv: Implement VLA stuff makes 78_vla_label and 79_vla_continue work.
2019-07-15 22:42:29 +03:00
EI(0x03, 3, 2, 8, addr); // ld sp, fc(s0)
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
ST_FUNC void gen_vla_alloc(CType *type, int align)
{
riscv: Implement VLA stuff makes 78_vla_label and 79_vla_continue work.
2019-07-15 22:42:29 +03:00
int rr = ireg(gv(RC_INT));
EI(0x13, 0, rr, rr, 15); // addi RR, RR, 15
EI(0x13, 7, rr, rr, -16); // andi, RR, RR, -16
riscv: Replace RR insn emitter with specific one instead of using o() directly. Makes the code a little easier to read.
2019-08-13 05:06:07 +03:00
ER(0x33, 0, 2, 2, rr, 0x20); // sub sp, sp, rr
riscv: Implement VLA stuff makes 78_vla_label and 79_vla_continue work.
2019-07-15 22:42:29 +03:00
vpop();
riscv64: Add skeleton target
2019-06-22 07:13:10 +03:00
}
#endif
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