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tinycc/tests/asmtest.S

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tccpp: treat gas comments in .S files as raw text, not tokens
2011-02-24 02:13:08 +03:00
# gas comment with ``gnu'' style quotes
asm test
2003-01-06 23:24:13 +03:00
/* some directive tests */
.byte 0xff
.byte 1, 2, 3
.short 1, 2, 3
.word 1, 2, 3
.long 1, 2, 3
.int 1, 2, 3
.align 8
.byte 1
asmtest: avoid testing against complex nop alignment in gas .align #,0x90 in gas ignores the 0x90 and outputs any kind of nop it feels like. the one avoided by this patch is a 7 byte nop, which gas has been doing since at least 1999: http://sourceware.org/ml/binutils/1999-10/msg00083.html In order to match what gas does, we would need to make code alignment target-specific, import a lot of code, and face the question: exactly which gas {version,target,tune} combo are we trying to match? see i386_align_code in: http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/config/tc-i386.c?annotate=1.460&cvsroot=src The smart noppery is turned on via the special casing of 0x90 at line 438 in md_do_align in: http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/config/tc-i386.h?annotate=1.1&cvsroot=src
2011-01-24 03:46:24 +03:00
/* .align 16, 0x90 gas is too clever for us with 0x90 fill */
tccasm: Accept .balign
2016-06-29 18:22:05 +03:00
.balign 4, 0x92
asmtest: avoid testing against complex nop alignment in gas .align #,0x90 in gas ignores the 0x90 and outputs any kind of nop it feels like. the one avoided by this patch is a 7 byte nop, which gas has been doing since at least 1999: http://sourceware.org/ml/binutils/1999-10/msg00083.html In order to match what gas does, we would need to make code alignment target-specific, import a lot of code, and face the question: exactly which gas {version,target,tune} combo are we trying to match? see i386_align_code in: http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/config/tc-i386.c?annotate=1.460&cvsroot=src The smart noppery is turned on via the special casing of 0x90 at line 438 in md_do_align in: http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/config/tc-i386.h?annotate=1.1&cvsroot=src
2011-01-24 03:46:24 +03:00
.align 16, 0x91 /* 0x91 tests the non-clever behaviour */
asm test
2003-01-06 23:24:13 +03:00
.skip 3
.skip 15, 0x90
update
2003-05-24 18:18:38 +04:00
.string "hello\0world"
tccasm: Don't ignore # in preprocessor directives Our preprocessor throws away # line-comments in asm mode. It did so also inside preprocessor directives, thereby removing stringification. Parse defines in non-asm mode (but retain '.' as identifier character inside macro definitions).
2016-08-25 17:40:50 +03:00
/* Macro expansion should work like with C, the #n shouldn't be parsed
as asm line comment */
#define __stringify(n) #n
#define stringify(n) __stringify(n)
.skip 8,0x90
.asciz stringify(BLA)
.skip 8,0x90
# 28 "asmtest.S" # a line directive (and a line comment)
movl %eax, %ebx # some more asm comment
asm test
2003-01-06 23:24:13 +03:00
/* some label tests */
L1:
movl %eax, %ebx
mov 0x10000, %eax
L2:
movl $L2 - L1, %ecx
var1:
nop ; nop ; nop ; nop
mov var1, %eax
/* instruction tests */
movl %eax, %ebx
mov 0x10000, %eax
mov 0x10000, %ax
mov 0x10000, %al
mov %al, 0x10000
mov $1, %edx
mov $1, %dx
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
mov $1, %cl
asm test
2003-01-06 23:24:13 +03:00
movb $2, 0x100(%ebx,%edx,2)
movw $2, 0x100(%ebx,%edx,2)
movl $2, 0x100(%ebx,%edx,2)
movl %eax, 0x100(%ebx,%edx,2)
movl 0x100(%ebx,%edx,2), %edx
movw %ax, 0x100(%ebx,%edx,2)
update
2004-10-18 04:12:31 +04:00
x86-64-asm: Clean up 64bit immediate support Fix it to actually be able to parse 64bit immediates (enlarge operand value type). Then, generally there's no need for accepting IM64 anywhere, except in the 0xba+r mov opcodes, so OP_IM is unnecessary, as is OPT_IMNO64. Improve the generated code a bit by preferring the 0xc7 opcode for im32->reg64, instead of the im64->reg64 form (which we therefore hardcode).
2016-05-12 00:47:02 +03:00
movw $0x1122,%si
movl $0x112233,%edx
x86-asm: Accept all 32bit immediates In particular don't care if they're signed or unsigned, they're all acceptable as immediates.
2016-08-24 18:50:23 +03:00
movl $0x80000000, %esi
movl $-0x7fffffff, %edi
x86-64-asm: Clean up 64bit immediate support Fix it to actually be able to parse 64bit immediates (enlarge operand value type). Then, generally there's no need for accepting IM64 anywhere, except in the 0xba+r mov opcodes, so OP_IM is unnecessary, as is OPT_IMNO64. Improve the generated code a bit by preferring the 0xc7 opcode for im32->reg64, instead of the im64->reg64 form (which we therefore hardcode).
2016-05-12 00:47:02 +03:00
#ifdef __x86_64__
mov $0x11223344,%rbx
movq $0x11223344,%rbx
mov $0x1122334455,%rbx
movq $0x1122334455,%rbx
movl $0x11334455,(%rbx)
#endif
update
2004-10-18 04:12:31 +04:00
mov %eax, 0x12(,%edx,2)
asm test
2003-01-06 23:24:13 +03:00
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
mov %cr3, %edx
mov %ecx, %cr3
movl %cr3, %eax
movl %tr3, %eax
movl %db3, %ebx
movl %dr6, %eax
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#else
mov %cr3, %rdx
mov %rcx, %cr3
movq %cr3, %rax
movq %db3, %rbx
movq %dr6, %rax
x86-64-asm: Implement high %cr registers
2016-08-06 23:48:24 +03:00
mov %cr8, %rsi
mov %rdi, %cr8
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#endif
asm test
2003-01-06 23:24:13 +03:00
movl %fs, %ecx
movl %ebx, %fs
x86-64-asm: Support high registers %r8 - %r15 This requires correctly handling the REX prefix. As bonus we now also support the four 8bit registers spl,bpl,sil,dil, which are decoded as ah,ch,dh,bh in non-long-mode (and require a REX prefix as well).
2016-08-04 05:47:03 +03:00
#ifdef __x86_64__
movq %r8, %r9
movq %r10, %r11
movq %r12, %r13
movq %r14, %r15
movq %rax, %r9
movq %r15, %rsi
inc %r9b
dec %r10w
not %r11d
negq %r12
decb %r13b
incw %r14w
notl %r15d
#endif
asm test
2003-01-06 23:24:13 +03:00
movsbl 0x1000, %eax
movsbw 0x1000, %ax
movswl 0x1000, %eax
movzbl 0x1000, %eax
movzbw 0x1000, %ax
movzwl 0x1000, %eax
movzb 0x1000, %eax
movzb 0x1000, %ax
x86-64-asm: Fix mov im64,rax encoding the avoidance of mov im32->reg64 wasn't working when reg64 was rax. While fixing this also fix instructions which had the REX prefix hardcoded in opcode and so didn't support extended registers which would have added another REX prefix.
2017-02-23 02:16:25 +03:00
mov $0x12345678,%eax
x86-64-asm: Add mov[sz]xq opcodes This adds the zero/sign-extending opcodes with 64bit destinations.
2016-05-12 01:57:02 +03:00
#ifdef __x86_64__
movzb 0x1000, %rax
movzbq 0x1000, %rbx
movsbq 0x1000, %rdx
movzwq 0x1000, %rdi
movswq 0x1000, %rdx
x86-64-asm: Fix mov im64,rax encoding the avoidance of mov im32->reg64 wasn't working when reg64 was rax. While fixing this also fix instructions which had the REX prefix hardcoded in opcode and so didn't support extended registers which would have added another REX prefix.
2017-02-23 02:16:25 +03:00
movslq %eax, %rcx
mov $0x12345678,%rax
mov $0x12345678,%rdx
mov $0x12345678,%r10
mov $0x123456789abcdef0,%rax
mov $0x123456789abcdef0,%rcx
mov $0x123456789abcdef0,%r11
x86-64-asm: Add mov[sz]xq opcodes This adds the zero/sign-extending opcodes with 64bit destinations.
2016-05-12 01:57:02 +03:00
#endif
asm test
2003-01-06 23:24:13 +03:00
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
pushl %eax
push %eax
push %cs
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#else
pushq %rax
push %rax
#endif
pushw %ax
asm test
2003-01-06 23:24:13 +03:00
push %gs
push $1
push $100
x86-64-asm: Fix ltr/str and push/pop operands str accepts rm16/r32/r64, and push/pop defaults to 64 when given memory operands (to 32 on i386).
2016-08-07 00:19:04 +03:00
push 0x42(%eax)
pop 0x43(%esi)
asm test
2003-01-06 23:24:13 +03:00
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
popl %eax
pop %eax
pop %ds
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#else
popq %rax
pop %rax
#endif
popw %ax
asm test
2003-01-06 23:24:13 +03:00
pop %fs
xchg %eax, %ecx
xchg %edx, %eax
xchg %bx, 0x10000
xchg 0x10000, %ebx
xchg 0x10000, %dl
in $100, %al
in $100, %ax
in $100, %eax
in %dx, %al
in %dx, %ax
in %dx, %eax
inb %dx
inw %dx
inl %dx
out %al, $100
out %ax, $100
out %eax, $100
/* NOTE: gas is bugged here, so size must be added */
outb %al, %dx
outw %ax, %dx
outl %eax, %dx
leal 0x1000(%ebx), %ecx
lea 0x1000(%ebx), %ecx
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
les 0x2000, %eax
lds 0x2000, %ebx
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
lss 0x2000, %edx
#endif
asm test
2003-01-06 23:24:13 +03:00
lfs 0x2000, %ecx
lgs 0x2000, %edx
addl $0x123, %eax
add $0x123, %ebx
x86-asm: Fix signed constants and opcode order Two things: negative constants were rejected (e.g. "add $-15,%eax"). Second the insn order was such that the arithmetic IM8S forms weren't used (always the IM32 ones). Switching them prefers those but requires a fix for size calculation in case the opcodes were OPC_ARITH and OPC_WLX (whose size starts with 1, not zero).
2016-05-14 05:33:41 +03:00
add $-16, %ecx
add $-0x123, %esi
x86-asm: Reject some invalid arith imm8 instruction There were two errors in the arithmetic imm8 instruction. They accept only REGW, and in case the user write a xxxb opcode that variant needs to be rejected as well (it's not automatically rejected by REGW in case the destination is memory).
2016-05-16 06:10:21 +03:00
add $1, %bx
add $1, %ebx
add $-1, %bx
add $-1, %ebx
add $127, %bx
addl $127, %ebx
addl $-128, %ebx
addl $-128, %ebx
addl $-129, %ebx
addl $128, %ebx
addl $255, %ebx
addl $256, %ebx
andb $0xf, %ah
andb $-15, %cl
xorb $127, %dh
cmpb $42, (%eax)
asm test
2003-01-06 23:24:13 +03:00
addl $0x123, 0x100
addl $0x123, 0x100(%ebx)
addl $0x123, 0x100(%ebx,%edx,2)
addl $0x123, 0x100(%esp)
tccasm: accept bracketed offset expressions
2011-02-02 02:53:48 +03:00
addl $0x123, (3*8)(%esp)
asm test
2003-01-06 23:24:13 +03:00
addl $0x123, (%ebp)
addl $0x123, (%esp)
cmpl $0x123, (%esp)
x86-64-asm: Support high registers %r8 - %r15 This requires correctly handling the REX prefix. As bonus we now also support the four 8bit registers spl,bpl,sil,dil, which are decoded as ah,ch,dh,bh in non-long-mode (and require a REX prefix as well).
2016-08-04 05:47:03 +03:00
#ifdef __x86_64__
xor %bl,%ah
xor %bl,%r8b
xor %r9b,%bl
xor %sil,%cl
add %eax,(%r8d)
add %ebx,(%r9)
add %edx,(%r10d,%r11d)
add %ecx,(%r12,%r13)
add %esi,(%r14,%r15,4)
add %edi,0x1000(%rbx,%r12,8)
add %r11,0x1000(%ebp,%r9d,8)
movb $12, %ah
movb $13, %bpl
movb $14, %dil
movb $15, %r12b
#endif
asm test
2003-01-06 23:24:13 +03:00
add %eax, (%ebx)
add (%ebx), %eax
or %dx, (%ebx)
or (%ebx), %si
add %cl, (%ebx)
add (%ebx), %dl
inc %edx
incl 0x10000
incb 0x10000
dec %dx
test $1, %al
test $1, %cl
testl $1, 0x1000
testb $1, 0x1000
testw $1, 0x1000
test %eax, %ebx
test %eax, 0x1000
test 0x1000, %edx
not %edx
notw 0x10000
notl 0x10000
notb 0x10000
neg %edx
negw 0x10000
negl 0x10000
negb 0x10000
imul %ecx
mul %edx
mulb %cl
imul %eax, %ecx
imul 0x1000, %cx
imul $10, %eax, %ecx
imul $10, %ax, %cx
imul $10, %eax
imul $0x1100000, %eax
imul $1, %eax
idivw 0x1000
div %ecx
div %bl
div %ecx, %eax
x86-asm: Fix signed constants and opcode order Two things: negative constants were rejected (e.g. "add $-15,%eax"). Second the insn order was such that the arithmetic IM8S forms weren't used (always the IM32 ones). Switching them prefers those but requires a fix for size calculation in case the opcodes were OPC_ARITH and OPC_WLX (whose size starts with 1, not zero).
2016-05-14 05:33:41 +03:00
and $15,%bx
and $-20,%edx
asm test
2003-01-06 23:24:13 +03:00
shl %edx
shl $10, %edx
shl %cl, %edx
shld $1, %eax, %edx
shld %cl, %eax, %edx
shld %eax, %edx
shrd $1, %eax, %edx
shrd %cl, %eax, %edx
shrd %eax, %edx
L4:
call 0x1000
call L4
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
call *%eax
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#else
call *%rax
#endif
asm test
2003-01-06 23:24:13 +03:00
call *0x1000
call func1
accept multiple comma separated symbols for .globl/.global directives, like gas does
2011-01-20 13:00:50 +03:00
.global L5,L6
L5:
L6:
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
lcall $0x100, $0x1000
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#else
lcall *0x100
lcall *(%rax)
#endif
asm test
2003-01-06 23:24:13 +03:00
jmp 0x1000
x86-64 asm: Remove useless jmp opcode Also remove the hacky mod/rm byte emission during disp/imm writing.
2016-05-11 19:56:19 +03:00
jmp *(%edi)
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
jmp *%eax
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#else
jmp *%rax
#endif
asm test
2003-01-06 23:24:13 +03:00
jmp *0x1000
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
ljmp $0x100, $0x1000
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#else
ljmp *0x100
ljmp *(%rdi)
x86-asm: More opcodes Some new opcodes and some aliases: ljmp[wl], prefetch{nta,t0,t1,t2}, bswap[lq], sysretq, swapgs.
2016-07-11 22:11:13 +03:00
ljmpl *(%esi)
ljmpw *(%esi)
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#endif
asm test
2003-01-06 23:24:13 +03:00
ret
ret $10
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
retl
i386-asm: accept retl as a synonym for ret
2011-01-21 12:35:28 +03:00
retl $10
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#else
retq
retq $10
#endif
asm test
2003-01-06 23:24:13 +03:00
lret
lret $10
enter $1234, $10
L3:
jo 0x1000
jnp 0x1001
jne 0x1002
jg 0x1003
jo L3
jnp L3
jne L3
jg L3
loopne L3
loopnz L3
loope L3
loopz L3
loop L3
jecxz L3
seto %al
Allow tcc to understand a setob,... opcodes as alias to seto,... PS: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20101122/112576.html This is fix PR8686 for llvm: accepting a 'b' suffix at the end of all the setcc instructions.
2015-01-06 22:59:19 +03:00
setc %al
setcb %al
asm test
2003-01-06 23:24:13 +03:00
setnp 0x1000
setl 0xaaaa
setg %dl
fadd
fadd %st(1), %st
tccasm: accept "fmul/fadd st(0),st(n)" (dietlibc ipow/atanh)
2011-02-02 02:49:37 +03:00
fadd %st(0), %st(1)
asm test
2003-01-06 23:24:13 +03:00
fadd %st(3)
tccasm: accept "fmul/fadd st(0),st(n)" (dietlibc ipow/atanh)
2011-02-02 02:49:37 +03:00
fmul %st(0),%st(0)
fmul %st(0),%st(1)
asm test
2003-01-06 23:24:13 +03:00
faddp %st(5)
faddp
faddp %st(1), %st
fadds 0x1000
fiadds 0x1002
faddl 0x1004
fiaddl 0x1006
fmul
fmul %st(1), %st
fmul %st(3)
fmulp %st(5)
fmulp
fmulp %st(1), %st
fmuls 0x1000
fimuls 0x1002
fmull 0x1004
fimull 0x1006
fsub
fsub %st(1), %st
fsub %st(3)
fsubp %st(5)
fsubp
fsubp %st(1), %st
fsubs 0x1000
fisubs 0x1002
fsubl 0x1004
fisubl 0x1006
fsubr
fsubr %st(1), %st
fsubr %st(3)
fsubrp %st(5)
fsubrp
fsubrp %st(1), %st
fsubrs 0x1000
fisubrs 0x1002
fsubrl 0x1004
fisubrl 0x1006
fdiv
fdiv %st(1), %st
fdiv %st(3)
fdivp %st(5)
fdivp
fdivp %st(1), %st
fdivs 0x1000
fidivs 0x1002
fdivl 0x1004
fidivl 0x1006
fcom %st(3)
fcoms 0x1000
ficoms 0x1002
fcoml 0x1004
ficoml 0x1006
fcomp %st(5)
fcomp
fcompp
fcomps 0x1000
ficomps 0x1002
fcompl 0x1004
ficompl 0x1006
fld %st(5)
fldl 0x1000
flds 0x1002
fildl 0x1004
fst %st(4)
fstp %st(6)
fstpt 0x1006
fbstp 0x1008
fxch
fxch %st(4)
fucom %st(6)
fucomp %st(3)
fucompp
finit
fninit
fldcw 0x1000
fnstcw 0x1002
fstcw 0x1002
fnstsw 0x1004
fix asmtest (somehow), update Makefiles
2009-07-06 23:11:19 +04:00
fnstsw (%eax)
asm test
2003-01-06 23:24:13 +03:00
fstsw 0x1004
fix asmtest (somehow), update Makefiles
2009-07-06 23:11:19 +04:00
fstsw (%eax)
asm test
2003-01-06 23:24:13 +03:00
fnclex
fclex
fnstenv 0x1000
fstenv 0x1000
fldenv 0x1000
fnsave 0x1002
fsave 0x1000
frstor 0x1000
ffree %st(7)
ffreep %st(6)
ftst
fxam
fld1
fldl2t
fldl2e
fldpi
fldlg2
fldln2
fldz
f2xm1
fyl2x
fptan
fpatan
fxtract
fprem1
fdecstp
fincstp
fprem
fyl2xp1
fsqrt
fsincos
frndint
fscale
fsin
fcos
fchs
fabs
fnop
fwait
bswap %edx
x86-asm: More opcodes Some new opcodes and some aliases: ljmp[wl], prefetch{nta,t0,t1,t2}, bswap[lq], sysretq, swapgs.
2016-07-11 22:11:13 +03:00
bswapl %ecx
asm test
2003-01-06 23:24:13 +03:00
xadd %ecx, %edx
xaddb %dl, 0x1000
xaddw %ax, 0x1000
xaddl %eax, 0x1000
cmpxchg %ecx, %edx
cmpxchgb %dl, 0x1000
cmpxchgw %ax, 0x1000
cmpxchgl %eax, 0x1000
invlpg 0x1000
cmpxchg8b 0x1002
x86-64-asm: Implement cmpxchg16b
2016-08-08 21:28:21 +03:00
#ifdef __x86_64__
cmpxchg16b (%rax)
x86-64-asm: Fix mov im64,rax encoding the avoidance of mov im32->reg64 wasn't working when reg64 was rax. While fixing this also fix instructions which had the REX prefix hardcoded in opcode and so didn't support extended registers which would have added another REX prefix.
2017-02-23 02:16:25 +03:00
cmpxchg16b (%r10,%r11)
x86-64-asm: Implement cmpxchg16b
2016-08-08 21:28:21 +03:00
#endif
asm test
2003-01-06 23:24:13 +03:00
fcmovb %st(5), %st
fcmove %st(5), %st
fcmovbe %st(5), %st
fcmovu %st(5), %st
fcmovnb %st(5), %st
fcmovne %st(5), %st
fcmovnbe %st(5), %st
fcmovnu %st(5), %st
fcomi %st(5), %st
fucomi %st(5), %st
fcomip %st(5), %st
fucomip %st(5), %st
cmovo 0x1000, %eax
cmovs 0x1000, %eax
cmovns %edx, %edi
x86: Improve cmov handling cmov can accept multi sizes, but is also a OPC_TEST opcode, deal with this.
2016-05-11 19:54:24 +03:00
cmovne %ax, %si
tccasm: Accept suffixed cmovCC The length suffix for cmovCC isn't necessary as the required register operands always allow length deduction. But let's be nice to users and accept them anyway. Do that without blowing up tables, which means we don't detect invalid suffixes for the given operands, but so be it.
2017-12-03 06:53:50 +03:00
cmovbw %ax, %di
cmovnbel %edx, %ecx
x86: Improve cmov handling cmov can accept multi sizes, but is also a OPC_TEST opcode, deal with this.
2016-05-11 19:54:24 +03:00
#ifdef __x86_64__
x86-asm: More opcodes Some new opcodes and some aliases: ljmp[wl], prefetch{nta,t0,t1,t2}, bswap[lq], sysretq, swapgs.
2016-07-11 22:11:13 +03:00
bswapq %rsi
x86-64-asm: Fix mov im64,rax encoding the avoidance of mov im32->reg64 wasn't working when reg64 was rax. While fixing this also fix instructions which had the REX prefix hardcoded in opcode and so didn't support extended registers which would have added another REX prefix.
2017-02-23 02:16:25 +03:00
bswapq %r10
x86: Improve cmov handling cmov can accept multi sizes, but is also a OPC_TEST opcode, deal with this.
2016-05-11 19:54:24 +03:00
cmovz %rdi,%rbx
tccasm: Accept suffixed cmovCC The length suffix for cmovCC isn't necessary as the required register operands always allow length deduction. But let's be nice to users and accept them anyway. Do that without blowing up tables, which means we don't detect invalid suffixes for the given operands, but so be it.
2017-12-03 06:53:50 +03:00
cmovpeq %rsi, %rdx
x86: Improve cmov handling cmov can accept multi sizes, but is also a OPC_TEST opcode, deal with this.
2016-05-11 19:54:24 +03:00
#endif
asm test
2003-01-06 23:24:13 +03:00
int $3
int $0x10
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
pusha
popa
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#endif
tccasm: Don't ignore # in preprocessor directives Our preprocessor throws away # line-comments in asm mode. It did so also inside preprocessor directives, thereby removing stringification. Parse defines in non-asm mode (but retain '.' as identifier character inside macro definitions).
2016-08-25 17:40:50 +03:00
clc # another comment
cld # a comment with embedded ' tick
asm test
2003-01-06 23:24:13 +03:00
cli
clts
cmc
lahf
sahf
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
pushfl
popfl
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#else
pushfq
popfq
#endif
asm test
2003-01-06 23:24:13 +03:00
pushf
popf
stc
std
sti
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
aaa
aas
daa
das
aad
aam
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
into
#endif
asm test
2003-01-06 23:24:13 +03:00
cbw
cwd
cwde
cdq
cbtw
cwtd
cwtl
cltd
leave
int3
iret
rsm
hlt
wait
nop
/* XXX: handle prefixes */
#if 0
aword
addr16
#endif
lock
rep
repe
repz
repne
repnz
tccasm: allow one-line prefix+op things like "rep stosb"
2011-02-02 02:37:58 +03:00
nop
lock ;negl (%eax)
wait ;pushf
rep ;stosb
repe ;lodsb
repz ;cmpsb
repne;movsb
repnz;outsb
/* handle one-line prefix + ops */
lock negl (%eax)
wait pushf
rep stosb
repe lodsb
repz cmpsb
repne movsb
repnz outsb
asm test
2003-01-06 23:24:13 +03:00
invd
wbinvd
cpuid
wrmsr
rdtsc
rdmsr
rdpmc
ud2
x86-64-asm: More opcodes Implement some more opcodes, syscall, sysret, lfence, mfence, sfence.
2016-06-30 17:14:32 +03:00
#ifdef __x86_64__
syscall
sysret
x86-asm: More opcodes Some new opcodes and some aliases: ljmp[wl], prefetch{nta,t0,t1,t2}, bswap[lq], sysretq, swapgs.
2016-07-11 22:11:13 +03:00
sysretq
x86-64-asm: More opcodes Implement some more opcodes, syscall, sysret, lfence, mfence, sfence.
2016-06-30 17:14:32 +03:00
lfence
mfence
sfence
x86-asm: More opcodes Some new opcodes and some aliases: ljmp[wl], prefetch{nta,t0,t1,t2}, bswap[lq], sysretq, swapgs.
2016-07-11 22:11:13 +03:00
prefetchnta 0x18(%rdx)
prefetcht0 (%rcx)
prefetcht1 (%rsi)
prefetcht2 (%rdi)
x86-asm: Implement prefetchw opcode
2016-07-11 23:06:27 +03:00
prefetchw (%rdi)
x86-asm: Implement clflush opcode
2016-07-11 18:25:18 +03:00
clflush 0x1000(%rax,%rcx)
x86-asm: Implement fxrstorq and fxsaveq
2016-07-11 19:53:44 +03:00
fxsaveq (%rdx)
x86-64-asm: Fix mov im64,rax encoding the avoidance of mov im32->reg64 wasn't working when reg64 was rax. While fixing this also fix instructions which had the REX prefix hardcoded in opcode and so didn't support extended registers which would have added another REX prefix.
2017-02-23 02:16:25 +03:00
fxsaveq (%r11)
x86-asm: Implement fxrstorq and fxsaveq
2016-07-11 19:53:44 +03:00
fxrstorq (%rcx)
x86-64-asm: Fix mov im64,rax encoding the avoidance of mov im32->reg64 wasn't working when reg64 was rax. While fixing this also fix instructions which had the REX prefix hardcoded in opcode and so didn't support extended registers which would have added another REX prefix.
2017-02-23 02:16:25 +03:00
fxrstorq (%r10)
x86-asm: Fix lar opcode operands lar can accept multiple sizes as well (wlx), like lsl. When using autosize it's important to look at the destination operand first; when it's a register that one determines the size, not the input operand.
2016-07-11 22:41:15 +03:00
x86-64-asm: More opcodes Implement some more opcodes, syscall, sysret, lfence, mfence, sfence.
2016-06-30 17:14:32 +03:00
#endif
asm test
2003-01-06 23:24:13 +03:00
x86-asm: Fix lar opcode operands lar can accept multiple sizes as well (wlx), like lsl. When using autosize it's important to look at the destination operand first; when it's a register that one determines the size, not the input operand.
2016-07-11 22:41:15 +03:00
lar %ax,%dx
lar %eax,%dx
lar %ax,%edx
lar %eax,%edx
tccasm: Don't ignore # in preprocessor directives Our preprocessor throws away # line-comments in asm mode. It did so also inside preprocessor directives, thereby removing stringification. Parse defines in non-asm mode (but retain '.' as identifier character inside macro definitions).
2016-08-25 17:40:50 +03:00
#ifdef __x86_64__
x86-asm: Fix lar opcode operands lar can accept multiple sizes as well (wlx), like lsl. When using autosize it's important to look at the destination operand first; when it's a register that one determines the size, not the input operand.
2016-07-11 22:41:15 +03:00
lar %ax,%rdx
lar %eax,%rdx
tccasm: Don't ignore # in preprocessor directives Our preprocessor throws away # line-comments in asm mode. It did so also inside preprocessor directives, thereby removing stringification. Parse defines in non-asm mode (but retain '.' as identifier character inside macro definitions).
2016-08-25 17:40:50 +03:00
#endif
asm test
2003-01-06 23:24:13 +03:00
emms
movd %edx, %mm3
movd 0x1000, %mm2
movd %mm4, %ecx
movd %mm5, 0x1000
movq 0x1000, %mm2
movq %mm4, 0x1000
pand 0x1000, %mm3
pand %mm4, %mm5
psllw $1, %mm6
psllw 0x1000, %mm7
psllw %mm2, %mm7
xlat
cmpsb
scmpw
insl
outsw
lodsb
slodl
movsb
movsl
smovb
scasb
sscaw
stosw
sstol
bsf 0x1000, %ebx
bsr 0x1000, %ebx
bt %edx, 0x1000
btl $2, 0x1000
btc %edx, 0x1000
btcl $2, 0x1000
btr %edx, 0x1000
btrl $2, 0x1000
bts %edx, 0x1000
btsl $2, 0x1000
update
2004-10-18 04:12:31 +04:00
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
asm test
2003-01-06 23:24:13 +03:00
boundl %edx, 0x10000
boundw %bx, 0x1000
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
asm test
2003-01-06 23:24:13 +03:00
arpl %bx, 0x1000
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#endif
asm test
2003-01-06 23:24:13 +03:00
lar 0x1000, %eax
lgdt 0x1000
lidt 0x1000
lldt 0x1000
sgdt 0x1000
sidt 0x1000
sldt 0x1000
x86-asm: Add [sl][ig]dtq opcodes GAS has alias lgdtq for lgdt (similar for saves and GDT). It doesn't have the same for LDT.
2016-07-11 20:57:39 +03:00
#ifdef __x86_64__
lgdtq 0x1000
lidtq 0x1000
sgdtq 0x1000
sidtq 0x1000
x86-asm: More opcodes Some new opcodes and some aliases: ljmp[wl], prefetch{nta,t0,t1,t2}, bswap[lq], sysretq, swapgs.
2016-07-11 22:11:13 +03:00
swapgs
x86-64-asm: Fix mov im64,rax encoding the avoidance of mov im32->reg64 wasn't working when reg64 was rax. While fixing this also fix instructions which had the REX prefix hardcoded in opcode and so didn't support extended registers which would have added another REX prefix.
2017-02-23 02:16:25 +03:00
str %rdx
str %r9
x86-asm: Add [sl][ig]dtq opcodes GAS has alias lgdtq for lgdt (similar for saves and GDT). It doesn't have the same for LDT.
2016-07-11 20:57:39 +03:00
#endif
lmsw 0x1000
lsl 0x1000, %ecx
ltr 0x1000
x86-64-asm: Fix ltr/str and push/pop operands str accepts rm16/r32/r64, and push/pop defaults to 64 when given memory operands (to 32 on i386).
2016-08-07 00:19:04 +03:00
ltr %si
asm test
2003-01-06 23:24:13 +03:00
smsw 0x1000
str 0x1000
x86-64-asm: Fix ltr/str and push/pop operands str accepts rm16/r32/r64, and push/pop defaults to 64 when given memory operands (to 32 on i386).
2016-08-07 00:19:04 +03:00
str %ecx
str %dx
asm test
2003-01-06 23:24:13 +03:00
verr 0x1000
verw 0x1000
update
2004-10-18 04:12:31 +04:00
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
update
2004-10-18 04:12:31 +04:00
push %ds
pushw %ds
pushl %ds
pop %ds
popw %ds
popl %ds
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#endif
update
2004-10-18 04:12:31 +04:00
fxsave 1(%ebx)
fxrstor 1(%ecx)
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#ifdef __i386__
update
2004-10-18 04:12:31 +04:00
pushl $1
[x86] Fix some asm problems A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.
2016-05-09 22:38:01 +03:00
#else
pushq $1
#endif
update
2004-10-18 04:12:31 +04:00
pushw $1
push $1
tccasm: define __ASSEMBLER__ for .S files, like gcc does
2011-02-02 02:26:21 +03:00
#ifdef __ASSEMBLER__ // should be defined, for S files
inc %eax
#endif
tccasm: support alternate .type syntaxes
2011-02-24 20:24:02 +03:00
tccgen: fix long long -> char/short cast This was causing assembler bugs in a tcc compiled by itself at i386-asm.c:352 when ExprValue.v was changed to uint64_t: if (op->e.v == (int8_t)op->e.v) op->type |= OP_IM8S; A general test case: #include <stdio.h> int main(int argc, char **argv) { long long ll = 4000; int i = (char)ll; printf("%d\n", i); return 0; } Output was "4000", now "-96". Also: add "asmtest2" as asmtest with tcc compiled by itself
2016-10-02 02:38:22 +03:00
#ifndef _WIN32
tccasm: support alternate .type syntaxes
2011-02-24 20:24:02 +03:00
ft1: ft2: ft3: ft4: ft5: ft6: ft7: ft8: ft9:
xor %eax, %eax
ret
.type ft1,STT_FUNC
.type ft2,@STT_FUNC
.type ft3,%STT_FUNC
.type ft4,"STT_FUNC"
.type ft5,function
.type ft6,@function
.type ft7,%function
.type ft8,"function"
tccgen: fix long long -> char/short cast This was causing assembler bugs in a tcc compiled by itself at i386-asm.c:352 when ExprValue.v was changed to uint64_t: if (op->e.v == (int8_t)op->e.v) op->type |= OP_IM8S; A general test case: #include <stdio.h> int main(int argc, char **argv) { long long ll = 4000; int i = (char)ll; printf("%d\n", i); return 0; } Output was "4000", now "-96". Also: add "asmtest2" as asmtest with tcc compiled by itself
2016-10-02 02:38:22 +03:00
#endif
tccasm: support alternate .type syntaxes
2011-02-24 20:24:02 +03:00
i386-asm: support "pause" opcode
2011-02-24 20:38:13 +03:00
pause
x86-asm: Fix signed constants and opcode order Two things: negative constants were rejected (e.g. "add $-15,%eax"). Second the insn order was such that the arithmetic IM8S forms weren't used (always the IM32 ones). Switching them prefers those but requires a fix for size calculation in case the opcodes were OPC_ARITH and OPC_WLX (whose size starts with 1, not zero).
2016-05-14 05:33:41 +03:00
.rept 6
nop
.endr
x86-asm: Add .fill test
2016-05-14 05:41:06 +03:00
.fill 4,1,0x90
x86-asm: Add more SSE2 instructions In particular those that are extensions of existing mmx (or sse1) instructions by a simple 0x66 prefix. There's one caveat for x86-64: as we don't yet correctly handle the 0xf3 prefix the movq mem64->xmm is wrong (tested in asmtest.S). Needs some refactoring of the instr_type member.
2016-05-15 07:54:42 +03:00
tccasm: Implement .pushsection and .popsection
2016-06-28 16:11:06 +03:00
.section .text.one,"ax"
nop
.previous
.pushsection .text.one,"ax"
nop
.pushsection .text.two,"ax"
nop
.popsection
.popsection
Accept more asm expressions In particular subtracting a defined symbol from current section makes the value PC relative, and .org accepts symbolic expressions as well, if the symbol is from the current section.
2016-06-29 16:57:32 +03:00
1: ud2
.pushsection __bug_table,"a"
.align 8
2: .long 1b - 2b
.long 0x600000 - 2b
.long 1b + 42
.long 43 + 1b
.long 2b + 144
.long 145 + 2b
.word 164, 0
.org 2b+32
tccasm: Don't ignore # in preprocessor directives Our preprocessor throws away # line-comments in asm mode. It did so also inside preprocessor directives, thereby removing stringification. Parse defines in non-asm mode (but retain '.' as identifier character inside macro definitions).
2016-08-25 17:40:50 +03:00
#ifdef __x86_64__
x86-64-asm: Accept expressions for .quad The x86-64 target has 64bit relocs, and hence can accept generic expressions for '.quad'.
2016-06-29 20:22:07 +03:00
.quad 1b
tccasm: Don't ignore # in preprocessor directives Our preprocessor throws away # line-comments in asm mode. It did so also inside preprocessor directives, thereby removing stringification. Parse defines in non-asm mode (but retain '.' as identifier character inside macro definitions).
2016-08-25 17:40:50 +03:00
#else
.long 1b
#endif
tccasm: Implement compare expressions I.e. implement < > <= >= == !=. Comparisons are signed and result is -1 if true, 0 if false.
2016-06-30 16:47:58 +03:00
.popsection
3: mov %eax,%ecx
4:
.pushsection .text.three, "ax"
nop
.skip (-((4b-3b) > 0) * 2) , 0x90
Accept more asm expressions In particular subtracting a defined symbol from current section makes the value PC relative, and .org accepts symbolic expressions as well, if the symbol is from the current section.
2016-06-29 16:57:32 +03:00
.popsection
tccasm: Implement .set sym, expr That, as well as "sym = expr", if expr contains symbols. Slightly tricky because a definition from .set is overridable, whereas proper definitions aren't. This doesn't yet allow using this for override tricks from C and global asm blocks because the symbol tables from C and asm are separate.
2016-08-07 05:27:32 +03:00
.globl overrideme
.weak overrideme
nop
.globl notimplemented
notimplemented:
ret
.set overrideme, notimplemented
overrideme = notimplemented
overrideme:
ret
x86-asm: Add more SSE2 instructions In particular those that are extensions of existing mmx (or sse1) instructions by a simple 0x66 prefix. There's one caveat for x86-64: as we don't yet correctly handle the 0xf3 prefix the movq mem64->xmm is wrong (tested in asmtest.S). Needs some refactoring of the instr_type member.
2016-05-15 07:54:42 +03:00
movd %esi, %mm1
movd %edi, %xmm2
movd (%ebx), %mm3
movd (%ebx), %xmm3
movd %mm1, %esi
movd %xmm2, %edi
movd %mm3, (%edx)
movd %xmm3, (%edx)
#ifdef __x86_64__
movd %rsi, %mm1
movd %rdi, %xmm2
movd (%rbx), %mm3
movd (%rbx), %xmm3
x86-64-asm: Support high registers %r8 - %r15 This requires correctly handling the REX prefix. As bonus we now also support the four 8bit registers spl,bpl,sil,dil, which are decoded as ah,ch,dh,bh in non-long-mode (and require a REX prefix as well).
2016-08-04 05:47:03 +03:00
movd %mm1, %r12
x86-asm: Add more SSE2 instructions In particular those that are extensions of existing mmx (or sse1) instructions by a simple 0x66 prefix. There's one caveat for x86-64: as we don't yet correctly handle the 0xf3 prefix the movq mem64->xmm is wrong (tested in asmtest.S). Needs some refactoring of the instr_type member.
2016-05-15 07:54:42 +03:00
movd %xmm2, %rdi
x86-64-asm: Support high registers %r8 - %r15 This requires correctly handling the REX prefix. As bonus we now also support the four 8bit registers spl,bpl,sil,dil, which are decoded as ah,ch,dh,bh in non-long-mode (and require a REX prefix as well).
2016-08-04 05:47:03 +03:00
movd %mm3, (%r8)
movd %xmm3, (%r13)
x86-asm: Add more SSE2 instructions In particular those that are extensions of existing mmx (or sse1) instructions by a simple 0x66 prefix. There's one caveat for x86-64: as we don't yet correctly handle the 0xf3 prefix the movq mem64->xmm is wrong (tested in asmtest.S). Needs some refactoring of the instr_type member.
2016-05-15 07:54:42 +03:00
#endif
movq (%ebp), %mm1
movq %mm2, (%edi)
x86-asm: Correct mem64->xmm movq Now we can express prefixes with 0x0fxx opcodes we can correct the movq mem64->xmm opcode, and restrict the movq xmm->mem64 movq to not invalidly accept mmx.
2016-05-15 20:07:13 +03:00
movq (%edi), %xmm3
x86-64-asm: Tidy
2016-05-15 20:20:41 +03:00
movq %mm4, %mm5
x86-asm: Add more SSE2 instructions In particular those that are extensions of existing mmx (or sse1) instructions by a simple 0x66 prefix. There's one caveat for x86-64: as we don't yet correctly handle the 0xf3 prefix the movq mem64->xmm is wrong (tested in asmtest.S). Needs some refactoring of the instr_type member.
2016-05-15 07:54:42 +03:00
#ifdef __x86_64__
movq %rcx, %mm1
movq %rdx, %xmm2
x86-64-asm: Fix mov im64,rax encoding the avoidance of mov im32->reg64 wasn't working when reg64 was rax. While fixing this also fix instructions which had the REX prefix hardcoded in opcode and so didn't support extended registers which would have added another REX prefix.
2017-02-23 02:16:25 +03:00
movq %r13, %xmm3
x86-asm: Add more SSE2 instructions In particular those that are extensions of existing mmx (or sse1) instructions by a simple 0x66 prefix. There's one caveat for x86-64: as we don't yet correctly handle the 0xf3 prefix the movq mem64->xmm is wrong (tested in asmtest.S). Needs some refactoring of the instr_type member.
2016-05-15 07:54:42 +03:00
/* movq mem64->xmm is encoded as f30f7e by GAS, but as
660f6e by tcc (which really is a movd and would need
a REX.W prefix to be movq). */
movq (%rsi), %xmm3
movq %mm1, %rdx
movq %xmm3, %rcx
movq %xmm4, (%rsi)
#endif
#define TEST_MMX_SSE(insn) \
insn %mm1, %mm2; \
insn %xmm2, %xmm3; \
insn (%ebx), %xmm3;
#define TEST_MMX_SSE_I8(insn) \
TEST_MMX_SSE(insn) \
insn $0x42, %mm4; \
insn $0x42, %xmm4;
TEST_MMX_SSE(packssdw)
TEST_MMX_SSE(packsswb)
TEST_MMX_SSE(packuswb)
TEST_MMX_SSE(paddb)
TEST_MMX_SSE(paddw)
TEST_MMX_SSE(paddd)
TEST_MMX_SSE(paddsb)
TEST_MMX_SSE(paddsw)
TEST_MMX_SSE(paddusb)
TEST_MMX_SSE(paddusw)
TEST_MMX_SSE(pand)
TEST_MMX_SSE(pandn)
TEST_MMX_SSE(pcmpeqb)
TEST_MMX_SSE(pcmpeqw)
TEST_MMX_SSE(pcmpeqd)
TEST_MMX_SSE(pcmpgtb)
TEST_MMX_SSE(pcmpgtw)
TEST_MMX_SSE(pcmpgtd)
TEST_MMX_SSE(pmaddwd)
TEST_MMX_SSE(pmulhw)
TEST_MMX_SSE(pmullw)
TEST_MMX_SSE(por)
TEST_MMX_SSE(psllw)
TEST_MMX_SSE_I8(psllw)
TEST_MMX_SSE(pslld)
TEST_MMX_SSE_I8(pslld)
TEST_MMX_SSE(psllq)
TEST_MMX_SSE_I8(psllq)
TEST_MMX_SSE(psraw)
TEST_MMX_SSE_I8(psraw)
TEST_MMX_SSE(psrad)
TEST_MMX_SSE_I8(psrad)
TEST_MMX_SSE(psrlw)
TEST_MMX_SSE_I8(psrlw)
TEST_MMX_SSE(psrld)
TEST_MMX_SSE_I8(psrld)
TEST_MMX_SSE(psrlq)
TEST_MMX_SSE_I8(psrlq)
TEST_MMX_SSE(psubb)
TEST_MMX_SSE(psubw)
TEST_MMX_SSE(psubd)
TEST_MMX_SSE(psubsb)
TEST_MMX_SSE(psubsw)
TEST_MMX_SSE(psubusb)
TEST_MMX_SSE(psubusw)
TEST_MMX_SSE(punpckhbw)
TEST_MMX_SSE(punpckhwd)
TEST_MMX_SSE(punpckhdq)
TEST_MMX_SSE(punpcklbw)
TEST_MMX_SSE(punpcklwd)
TEST_MMX_SSE(punpckldq)
TEST_MMX_SSE(pxor)
cvtpi2ps %mm1, %xmm2
cvtpi2ps (%ebx), %xmm2
TEST_MMX_SSE(pmaxsw)
TEST_MMX_SSE(pmaxub)
TEST_MMX_SSE(pminsw)
TEST_MMX_SSE(pminub)
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