Leon Alrae f31b035a9f target-mips: correctly handle access to unimplemented CP0 register
Release 6 limits the number of cases where software can cause UNDEFINED or
UNPREDICTABLE behaviour. In this case, when accessing reserved / unimplemented
CP0 register, writes are ignored and reads return 0.

In pre-R6 the behaviour is not specified, but generating RI exception is not
what the real HW does.

Additionally, remove CP0 Random register as it became reserved in Release 6.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03 11:48:34 +00:00
2014-11-03 11:48:34 +00:00
2014-09-25 13:34:03 +01:00
2014-11-02 13:30:00 +01:00
2014-10-23 15:34:02 +02:00
2014-10-24 12:19:11 +01:00
2014-09-26 13:37:06 -04:00
2014-09-26 13:37:06 -04:00
2014-10-10 14:07:08 +01:00
2014-09-26 09:34:39 +01:00
2014-10-24 12:19:11 +01:00
2014-09-22 11:39:45 +01:00
2014-09-22 11:39:45 +01:00
2014-10-02 09:58:14 +02:00
2014-10-27 14:09:27 +00:00

Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org

- QEMU team
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