target-alpha: Use cpu_exec_interrupt qom hook
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-12-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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32
cpu-exec.c
32
cpu-exec.c
@ -597,38 +597,6 @@ int cpu_exec(CPUArchState *env)
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cc->do_interrupt(cpu);
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next_tb = 0;
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}
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#elif defined(TARGET_ALPHA)
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{
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int idx = -1;
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/* ??? This hard-codes the OSF/1 interrupt levels. */
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switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
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case 0 ... 3:
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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idx = EXCP_DEV_INTERRUPT;
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}
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/* FALLTHRU */
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case 4:
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if (interrupt_request & CPU_INTERRUPT_TIMER) {
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idx = EXCP_CLK_INTERRUPT;
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}
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/* FALLTHRU */
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case 5:
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if (interrupt_request & CPU_INTERRUPT_SMP) {
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idx = EXCP_SMP_INTERRUPT;
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}
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/* FALLTHRU */
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case 6:
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if (interrupt_request & CPU_INTERRUPT_MCHK) {
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idx = EXCP_MCHK;
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}
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}
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if (idx >= 0) {
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cpu->exception_index = idx;
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env->error_code = 0;
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cc->do_interrupt(cpu);
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next_tb = 0;
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}
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}
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#endif
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/* The target hook has 3 exit conditions:
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False when the interrupt isn't processed,
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@ -79,6 +79,7 @@ extern const struct VMStateDescription vmstate_alpha_cpu;
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#endif
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void alpha_cpu_do_interrupt(CPUState *cpu);
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bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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@ -284,6 +284,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
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cc->class_by_name = alpha_cpu_class_by_name;
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cc->has_work = alpha_cpu_has_work;
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cc->do_interrupt = alpha_cpu_do_interrupt;
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cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt;
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cc->dump_state = alpha_cpu_dump_state;
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cc->set_pc = alpha_cpu_set_pc;
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cc->gdb_read_register = alpha_cpu_gdb_read_register;
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@ -470,6 +470,50 @@ void alpha_cpu_do_interrupt(CPUState *cs)
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#endif /* !USER_ONLY */
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}
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bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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CPUAlphaState *env = &cpu->env;
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int idx = -1;
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/* We never take interrupts while in PALmode. */
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if (env->pal_mode) {
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return false;
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}
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/* Fall through the switch, collecting the highest priority
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interrupt that isn't masked by the processor status IPL. */
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/* ??? This hard-codes the OSF/1 interrupt levels. */
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switch (env->ps & PS_INT_MASK) {
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case 0 ... 3:
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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idx = EXCP_DEV_INTERRUPT;
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}
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/* FALLTHRU */
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case 4:
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if (interrupt_request & CPU_INTERRUPT_TIMER) {
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idx = EXCP_CLK_INTERRUPT;
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}
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/* FALLTHRU */
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case 5:
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if (interrupt_request & CPU_INTERRUPT_SMP) {
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idx = EXCP_SMP_INTERRUPT;
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}
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/* FALLTHRU */
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case 6:
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if (interrupt_request & CPU_INTERRUPT_MCHK) {
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idx = EXCP_MCHK;
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}
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}
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if (idx >= 0) {
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cs->exception_index = idx;
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env->error_code = 0;
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alpha_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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int flags)
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{
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