Alistair Francis dc4d4aaee3 riscv: spike: Remove target macro conditionals ... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com		2020-12-17 21:56:44 -08:00
..
boot.c	hw/riscv: Expand the is 32-bit check to support more CPUs	2020-12-17 21:56:43 -08:00
Kconfig	hw/riscv: microchip_pfsoc: Connect the SYSREG module	2020-11-03 07:17:23 -08:00
meson.build	hw/riscv: Always build riscv_hart.c	2020-09-09 15:54:19 -07:00
microchip_pfsoc.c	hw/riscv: microchip_pfsoc: add QSPI NOR flash	2020-12-17 21:56:43 -08:00
numa.c	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
sifive_e.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
sifive_u.c	hw/riscv: sifive_u: Add UART1 DT node in the generated DTB	2020-12-17 21:56:43 -08:00
spike.c	riscv: spike: Remove target macro conditionals	2020-12-17 21:56:44 -08:00
virt.c	vl: make qemu_get_machine_opts static	2020-12-15 12:51:55 -05:00