mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

riscv: spike: Remove target macro conditionals

Browse Source 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2020-12-16 10:22:32 -08:00
parent c0a635f397
commit dc4d4aaee3
2 changed files with 1 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/riscv/spike.c
View File

@ -317,7 +317,7 @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
mc->init = spike_board_init;
mc->max_cpus = SPIKE_CPUS_MAX;
mc->is_default = true;
mc->default_cpu_type = SPIKE_V1_10_0_CPU;
mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;

6
include/hw/riscv/spike.h
View File

@ -47,10 +47,4 @@ enum {
SPIKE_DRAM
};
#if defined(TARGET_RISCV32)
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
#endif
#endif