hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
We add common helper routines which can be shared by RISC-V multi-socket NUMA machines. We have two types of helpers: 1. riscv_socket_xyz() - These helper assist managing multiple sockets irrespective whether QEMU NUMA is enabled/disabled 2. riscv_numa_xyz() - These helpers assist in providing necessary QEMU machine callbacks for QEMU NUMA emulation Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-4-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
Alistair Francis
parent
c9270e10a5
commit
83fcaefd9d
@ -1,5 +1,6 @@
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riscv_ss = ss.source_set()
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riscv_ss.add(files('boot.c'))
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riscv_ss.add(files('numa.c'))
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riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
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riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
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242
hw/riscv/numa.c
Normal file
242
hw/riscv/numa.c
Normal file
@ -0,0 +1,242 @@
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/*
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* QEMU RISC-V NUMA Helper
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*
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/qdev-properties.h"
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#include "hw/riscv/numa.h"
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#include "sysemu/device_tree.h"
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static bool numa_enabled(const MachineState *ms)
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{
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return (ms->numa_state && ms->numa_state->num_nodes) ? true : false;
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}
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int riscv_socket_count(const MachineState *ms)
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{
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return (numa_enabled(ms)) ? ms->numa_state->num_nodes : 1;
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}
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int riscv_socket_first_hartid(const MachineState *ms, int socket_id)
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{
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int i, first_hartid = ms->smp.cpus;
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if (!numa_enabled(ms)) {
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return (!socket_id) ? 0 : -1;
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}
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for (i = 0; i < ms->smp.cpus; i++) {
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if (ms->possible_cpus->cpus[i].props.node_id != socket_id) {
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continue;
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}
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if (i < first_hartid) {
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first_hartid = i;
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}
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}
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return (first_hartid < ms->smp.cpus) ? first_hartid : -1;
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}
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int riscv_socket_last_hartid(const MachineState *ms, int socket_id)
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{
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int i, last_hartid = -1;
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if (!numa_enabled(ms)) {
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return (!socket_id) ? ms->smp.cpus - 1 : -1;
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}
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for (i = 0; i < ms->smp.cpus; i++) {
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if (ms->possible_cpus->cpus[i].props.node_id != socket_id) {
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continue;
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}
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if (i > last_hartid) {
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last_hartid = i;
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}
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}
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return (last_hartid < ms->smp.cpus) ? last_hartid : -1;
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}
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int riscv_socket_hart_count(const MachineState *ms, int socket_id)
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{
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int first_hartid, last_hartid;
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if (!numa_enabled(ms)) {
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return (!socket_id) ? ms->smp.cpus : -1;
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}
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first_hartid = riscv_socket_first_hartid(ms, socket_id);
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if (first_hartid < 0) {
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return -1;
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}
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last_hartid = riscv_socket_last_hartid(ms, socket_id);
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if (last_hartid < 0) {
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return -1;
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}
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if (first_hartid > last_hartid) {
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return -1;
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}
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return last_hartid - first_hartid + 1;
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}
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bool riscv_socket_check_hartids(const MachineState *ms, int socket_id)
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{
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int i, first_hartid, last_hartid;
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if (!numa_enabled(ms)) {
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return (!socket_id) ? true : false;
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}
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first_hartid = riscv_socket_first_hartid(ms, socket_id);
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if (first_hartid < 0) {
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return false;
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}
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last_hartid = riscv_socket_last_hartid(ms, socket_id);
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if (last_hartid < 0) {
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return false;
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}
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for (i = first_hartid; i <= last_hartid; i++) {
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if (ms->possible_cpus->cpus[i].props.node_id != socket_id) {
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return false;
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}
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}
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return true;
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}
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uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id)
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{
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int i;
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uint64_t mem_offset = 0;
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if (!numa_enabled(ms)) {
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return 0;
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}
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for (i = 0; i < ms->numa_state->num_nodes; i++) {
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if (i == socket_id) {
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break;
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}
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mem_offset += ms->numa_state->nodes[i].node_mem;
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}
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return (i == socket_id) ? mem_offset : 0;
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}
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uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id)
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{
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if (!numa_enabled(ms)) {
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return (!socket_id) ? ms->ram_size : 0;
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}
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return (socket_id < ms->numa_state->num_nodes) ?
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ms->numa_state->nodes[socket_id].node_mem : 0;
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}
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void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
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const char *node_name, int socket_id)
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{
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if (numa_enabled(ms)) {
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qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id);
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}
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}
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void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt)
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{
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int i, j, idx;
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uint32_t *dist_matrix, dist_matrix_size;
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if (numa_enabled(ms) && ms->numa_state->have_numa_distance) {
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dist_matrix_size = riscv_socket_count(ms) * riscv_socket_count(ms);
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dist_matrix_size *= (3 * sizeof(uint32_t));
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dist_matrix = g_malloc0(dist_matrix_size);
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for (i = 0; i < riscv_socket_count(ms); i++) {
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for (j = 0; j < riscv_socket_count(ms); j++) {
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idx = (i * riscv_socket_count(ms) + j) * 3;
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dist_matrix[idx + 0] = cpu_to_be32(i);
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dist_matrix[idx + 1] = cpu_to_be32(j);
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dist_matrix[idx + 2] =
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cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
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}
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}
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qemu_fdt_add_subnode(fdt, "/distance-map");
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qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
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"numa-distance-map-v1");
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qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
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dist_matrix, dist_matrix_size);
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g_free(dist_matrix);
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}
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}
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CpuInstanceProperties
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riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
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{
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MachineClass *mc = MACHINE_GET_CLASS(ms);
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const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
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assert(cpu_index < possible_cpus->len);
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return possible_cpus->cpus[cpu_index].props;
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}
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int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx)
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{
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int64_t nidx = 0;
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if (ms->numa_state->num_nodes) {
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nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
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if (ms->numa_state->num_nodes <= nidx) {
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nidx = ms->numa_state->num_nodes - 1;
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}
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}
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return nidx;
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}
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const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms)
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{
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int n;
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unsigned int max_cpus = ms->smp.max_cpus;
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if (ms->possible_cpus) {
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assert(ms->possible_cpus->len == max_cpus);
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return ms->possible_cpus;
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}
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ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
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sizeof(CPUArchId) * max_cpus);
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ms->possible_cpus->len = max_cpus;
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for (n = 0; n < ms->possible_cpus->len; n++) {
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ms->possible_cpus->cpus[n].type = ms->cpu_type;
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ms->possible_cpus->cpus[n].arch_id = n;
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ms->possible_cpus->cpus[n].props.has_core_id = true;
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ms->possible_cpus->cpus[n].props.core_id = n;
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}
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return ms->possible_cpus;
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}
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113
include/hw/riscv/numa.h
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113
include/hw/riscv/numa.h
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@ -0,0 +1,113 @@
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/*
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* QEMU RISC-V NUMA Helper
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*
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_NUMA_H
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#define RISCV_NUMA_H
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#include "hw/sysbus.h"
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#include "sysemu/numa.h"
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/**
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* riscv_socket_count:
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* @ms: pointer to machine state
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*
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* Returns: number of sockets for a numa system and 1 for a non-numa system
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*/
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int riscv_socket_count(const MachineState *ms);
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/**
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* riscv_socket_first_hartid:
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* @ms: pointer to machine state
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* @socket_id: socket index
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*
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* Returns: first hartid for a valid socket and -1 for an invalid socket
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*/
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int riscv_socket_first_hartid(const MachineState *ms, int socket_id);
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/**
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* riscv_socket_last_hartid:
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* @ms: pointer to machine state
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* @socket_id: socket index
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*
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* Returns: last hartid for a valid socket and -1 for an invalid socket
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*/
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int riscv_socket_last_hartid(const MachineState *ms, int socket_id);
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/**
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* riscv_socket_hart_count:
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* @ms: pointer to machine state
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* @socket_id: socket index
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*
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* Returns: number of harts for a valid socket and -1 for an invalid socket
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*/
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int riscv_socket_hart_count(const MachineState *ms, int socket_id);
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/**
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* riscv_socket_mem_offset:
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* @ms: pointer to machine state
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* @socket_id: socket index
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*
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* Returns: offset of ram belonging to given socket
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*/
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uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id);
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/**
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* riscv_socket_mem_size:
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* @ms: pointer to machine state
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* @socket_id: socket index
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*
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* Returns: size of ram belonging to given socket
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*/
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uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id);
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/**
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* riscv_socket_check_hartids:
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* @ms: pointer to machine state
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* @socket_id: socket index
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*
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* Returns: true if hardids belonging to given socket are contiguous else false
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*/
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bool riscv_socket_check_hartids(const MachineState *ms, int socket_id);
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/**
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* riscv_socket_fdt_write_id:
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* @ms: pointer to machine state
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* @socket_id: socket index
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*
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* Write NUMA node-id FDT property for given FDT node
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*/
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void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
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const char *node_name, int socket_id);
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/**
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* riscv_socket_fdt_write_distance_matrix:
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* @ms: pointer to machine state
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* @socket_id: socket index
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*
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* Write NUMA distance matrix in FDT for given machine
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*/
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void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt);
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CpuInstanceProperties
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riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index);
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int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx);
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const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms);
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#endif /* RISCV_NUMA_H */
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