LIU Zhiwei d3842924cf target/riscv: vector bitwise logical instructions ... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-14-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-07-02 09:19:33 -07:00
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trans_privileged.inc.c	target/riscv: Move the hfence instructions to the rvh decode	2020-06-19 08:24:07 -07:00
trans_rva.inc.c	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
trans_rvd.inc.c	target/riscv: fsd/fsw doesn't dirty FP state	2020-01-16 10:03:08 -08:00
trans_rvf.inc.c	riscv: Add helper to make NaN-boxing for FP register	2020-06-19 08:24:07 -07:00
trans_rvh.inc.c	target/riscv: Implement checks for hfence	2020-06-19 08:24:07 -07:00
trans_rvi.inc.c	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-22 00:26:39 -07:00
trans_rvv.inc.c	target/riscv: vector bitwise logical instructions	2020-07-02 09:19:33 -07:00