LIU Zhiwei d3842924cf target/riscv: vector bitwise logical instructions ... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-14-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-07-02 09:19:33 -07:00
..
alpha	accel/tcg: Relax va restrictions on 64-bit guests	2020-05-15 15:25:16 +01:00
arm	target/arm: Enable MTE	2020-06-26 14:32:24 +01:00
cris
hppa	softfloat: Name compare relation enum	2020-05-19 08:41:45 -07:00
i386	i386: Mask SVM features if nested SVM is disabled	2020-06-26 09:39:40 -04:00
lm32
m68k	softfloat: merge floatx80_mod and floatx80_rem	2020-06-26 09:39:37 -04:00
microblaze
mips	hw/mips: Implement the kvm_type() hook in MachineClass	2020-06-27 19:35:39 +02:00
moxie
nios2
openrisc	softfloat: Name compare relation enum	2020-05-19 08:41:45 -07:00
ppc	target/ppc: Remove TIDR from POWER10 processor	2020-06-26 09:22:30 +10:00
riscv	target/riscv: vector bitwise logical instructions	2020-07-02 09:19:33 -07:00
rx
s390x	vfio-ccw: Add support for the schib region	2020-06-18 12:13:54 +02:00
sh4
sparc	target/sparc/int32_helper: Extract and use excp_name_str()	2020-06-09 09:21:10 +02:00
tilegx
tricore	target/tricore: Implement gdbstub	2020-06-01 16:55:13 +02:00
unicore32	target/unicore32: Prefer qemu_semihosting_log_out() over curses	2020-06-09 19:58:53 +02:00
xtensa	target/xtensa fixes for 5.1:	2020-06-25 21:20:45 +01:00