LIU Zhiwei d3842924cf target/riscv: vector bitwise logical instructions ... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-14-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-07-02 09:19:33 -07:00
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insn_trans	target/riscv: vector bitwise logical instructions	2020-07-02 09:19:33 -07:00
cpu_bits.h	target/riscv: support vector extension csr	2020-07-02 09:19:32 -07:00
cpu_helper.c	target/riscv: Report errors validating 2nd-stage PTEs	2020-06-19 08:24:07 -07:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: implementation-defined constant parameters	2020-07-02 09:19:32 -07:00
cpu.h	target/riscv: add vector configure instruction	2020-07-02 09:19:32 -07:00
csr.c	target/riscv: support vector extension csr	2020-07-02 09:19:32 -07:00
fpu_helper.c
gdbstub.c
helper.h	target/riscv: vector bitwise logical instructions	2020-07-02 09:19:33 -07:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode	target/riscv: add vector amo operations	2020-07-02 09:19:33 -07:00
insn32.decode	target/riscv: vector bitwise logical instructions	2020-07-02 09:19:33 -07:00
instmap.h
internals.h	target/riscv: add vector amo operations	2020-07-02 09:19:33 -07:00
Makefile.objs	target/riscv: add vector configure instruction	2020-07-02 09:19:32 -07:00
monitor.c
op_helper.c	target/riscv: Implement checks for hfence	2020-06-19 08:24:07 -07:00
pmp.c	target/riscv: Use a smaller guess size for no-MMU PMP	2020-06-19 08:24:07 -07:00
pmp.h
trace-events
translate.c	target/riscv: add vector stride load and store instructions	2020-07-02 09:19:32 -07:00
vector_helper.c	target/riscv: vector bitwise logical instructions	2020-07-02 09:19:33 -07:00