Michael Clark bb72692cbd SiFive RISC-V UART Device ... QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>		2018-03-07 08:30:28 +13:00
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riscv_hart.h	RISC-V HART Array	2018-03-07 08:30:28 +13:00
riscv_htif.h	RISC-V HTIF Console	2018-03-07 08:30:28 +13:00
sifive_clint.h	SiFive RISC-V CLINT Block	2018-03-07 08:30:28 +13:00
sifive_plic.h	SiFive RISC-V PLIC Block	2018-03-07 08:30:28 +13:00
sifive_test.h	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_uart.h	SiFive RISC-V UART Device	2018-03-07 08:30:28 +13:00
spike.h	RISC-V Spike Machines	2018-03-07 08:30:28 +13:00
virt.h	RISC-V VirtIO Machine	2018-03-07 08:30:28 +13:00