RISC-V VirtIO Machine
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
This commit is contained in:
Michael Clark
parent
88a07990fa
commit
04331d0b56
420
hw/riscv/virt.c
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420
hw/riscv/virt.c
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/*
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* QEMU RISC-V VirtIO Board
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* RISC-V machine with 16550a UART and VirtIO MMIO
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_htif.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/sifive_test.h"
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#include "hw/riscv/virt.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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#include "exec/address-spaces.h"
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#include "elf.h"
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} virt_memmap[] = {
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[VIRT_DEBUG] = { 0x0, 0x100 },
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[VIRT_MROM] = { 0x1000, 0x2000 },
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[VIRT_TEST] = { 0x4000, 0x1000 },
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[VIRT_CLINT] = { 0x2000000, 0x10000 },
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[VIRT_PLIC] = { 0xc000000, 0x4000000 },
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[VIRT_UART0] = { 0x10000000, 0x100 },
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[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
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[VIRT_DRAM] = { 0x80000000, 0x0 },
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};
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static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
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{
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int i;
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for (i = 0; i < (len >> 2); i++) {
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stl_phys(&address_space_memory, pa + (i << 2), rom[i]);
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}
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}
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static uint64_t identity_translate(void *opaque, uint64_t addr)
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{
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return addr;
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}
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static uint64_t load_kernel(const char *kernel_filename)
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{
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uint64_t kernel_entry, kernel_high;
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if (load_elf(kernel_filename, identity_translate, NULL,
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&kernel_entry, NULL, &kernel_high,
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0, ELF_MACHINE, 1, 0) < 0) {
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error_report("qemu: could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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return kernel_entry;
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}
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static hwaddr load_initrd(const char *filename, uint64_t mem_size,
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uint64_t kernel_entry, hwaddr *start)
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{
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int size;
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/* We want to put the initrd far enough into RAM that when the
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* kernel is uncompressed it will not clobber the initrd. However
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* on boards without much RAM we must ensure that we still leave
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* enough room for a decent sized initrd, and on boards with large
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* amounts of RAM we must avoid the initrd being so far up in RAM
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* that it is outside lowmem and inaccessible to the kernel.
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* So for boards with less than 256MB of RAM we put the initrd
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* halfway into RAM, and for boards with 256MB of RAM or more we put
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* the initrd at 128MB.
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*/
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*start = kernel_entry + MIN(mem_size / 2, 128 * 1024 * 1024);
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size = load_ramdisk(filename, *start, mem_size - *start);
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if (size == -1) {
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size = load_image_targphys(filename, *start, mem_size - *start);
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if (size == -1) {
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error_report("qemu: could not load ramdisk '%s'", filename);
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exit(1);
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}
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}
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return *start + size;
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}
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static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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void *fdt;
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int cpu;
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uint32_t *cells;
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char *nodename;
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uint32_t plic_phandle, phandle = 1;
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int i;
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "riscv-virtio-soc");
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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nodename = g_strdup_printf("/memory@%lx",
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(long)memmap[VIRT_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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int cpu_phandle = phandle++;
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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qemu_fdt_add_subnode(fdt, intc);
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qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
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qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
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qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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g_free(isa);
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g_free(intc);
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g_free(nodename);
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}
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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(long)memmap[VIRT_CLINT].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_CLINT].base,
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0x0, memmap[VIRT_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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plic_phandle = phandle++;
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
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(long)memmap[VIRT_PLIC].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_PLIC].base,
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0x0, memmap[VIRT_PLIC].size);
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qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
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qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
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qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
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qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
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plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
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g_free(cells);
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g_free(nodename);
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for (i = 0; i < VIRTIO_COUNT; i++) {
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nodename = g_strdup_printf("/virtio_mmio@%lx",
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(long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
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0x0, memmap[VIRT_VIRTIO].size);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/test@%lx",
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(long)memmap[VIRT_TEST].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_TEST].base,
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0x0, memmap[VIRT_TEST].size);
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nodename = g_strdup_printf("/uart@%lx",
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(long)memmap[VIRT_UART0].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_UART0].base,
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0x0, memmap[VIRT_UART0].size);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);
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qemu_fdt_add_subnode(fdt, "/chosen");
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qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
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qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
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g_free(nodename);
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return fdt;
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}
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static void riscv_virt_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = virt_memmap;
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RISCVVirtState *s = g_new0(RISCVVirtState, 1);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
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char *plic_hart_config;
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size_t plic_hart_config_len;
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int i;
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void *fdt;
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/* Initialize SOC */
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object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
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object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
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&error_abort);
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object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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/* register system main memory (actual RAM) */
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memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
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main_mem);
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/* create device tree */
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fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
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/* boot rom */
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memory_region_init_ram(boot_rom, NULL, "riscv_virt_board.bootrom",
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s->fdt_size + 0x2000, &error_fatal);
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memory_region_add_subregion(system_memory, 0x0, boot_rom);
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if (machine->kernel_filename) {
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uint64_t kernel_entry = load_kernel(machine->kernel_filename);
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if (machine->initrd_filename) {
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hwaddr start;
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hwaddr end = load_initrd(machine->initrd_filename,
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machine->ram_size, kernel_entry,
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&start);
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qemu_fdt_setprop_cell(fdt, "/chosen",
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"linux,initrd-start", start);
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qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
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end);
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}
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}
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/* reset vector */
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uint32_t reset_vec[8] = {
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0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
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0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
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0xf1402573, /* csrr a0, mhartid */
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#if defined(TARGET_RISCV32)
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0x0182a283, /* lw t0, 24(t0) */
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#elif defined(TARGET_RISCV64)
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0x0182b283, /* ld t0, 24(t0) */
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#endif
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0x00028067, /* jr t0 */
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0x00000000,
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memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base */
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0x00000000,
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/* dtb: */
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};
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/* copy in the reset vector */
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copy_le32_to_phys(ROM_BASE, reset_vec, sizeof(reset_vec));
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/* copy in the device tree */
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qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
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cpu_physical_memory_write(ROM_BASE + sizeof(reset_vec),
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s->fdt, s->fdt_size);
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/* create PLIC hart topology configuration string */
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plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
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plic_hart_config = g_malloc0(plic_hart_config_len);
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for (i = 0; i < smp_cpus; i++) {
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if (i != 0) {
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strncat(plic_hart_config, ",", plic_hart_config_len);
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}
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strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
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plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
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}
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/* MMIO */
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||||
s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
|
||||
plic_hart_config,
|
||||
VIRT_PLIC_NUM_SOURCES,
|
||||
VIRT_PLIC_NUM_PRIORITIES,
|
||||
VIRT_PLIC_PRIORITY_BASE,
|
||||
VIRT_PLIC_PENDING_BASE,
|
||||
VIRT_PLIC_ENABLE_BASE,
|
||||
VIRT_PLIC_ENABLE_STRIDE,
|
||||
VIRT_PLIC_CONTEXT_BASE,
|
||||
VIRT_PLIC_CONTEXT_STRIDE,
|
||||
memmap[VIRT_PLIC].size);
|
||||
sifive_clint_create(memmap[VIRT_CLINT].base,
|
||||
memmap[VIRT_CLINT].size, smp_cpus,
|
||||
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
|
||||
sifive_test_create(memmap[VIRT_TEST].base);
|
||||
|
||||
for (i = 0; i < VIRTIO_COUNT; i++) {
|
||||
sysbus_create_simple("virtio-mmio",
|
||||
memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
|
||||
SIFIVE_PLIC(s->plic)->irqs[VIRTIO_IRQ + i]);
|
||||
}
|
||||
|
||||
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
|
||||
0, SIFIVE_PLIC(s->plic)->irqs[UART0_IRQ], 399193,
|
||||
serial_hds[0], DEVICE_LITTLE_ENDIAN);
|
||||
}
|
||||
|
||||
static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void riscv_virt_board_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
||||
k->init = riscv_virt_board_sysbus_device_init;
|
||||
}
|
||||
|
||||
static const TypeInfo riscv_virt_board_device = {
|
||||
.name = TYPE_RISCV_VIRT_BOARD,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(RISCVVirtState),
|
||||
.class_init = riscv_virt_board_class_init,
|
||||
};
|
||||
|
||||
static void riscv_virt_board_machine_init(MachineClass *mc)
|
||||
{
|
||||
mc->desc = "RISC-V VirtIO Board (Privileged spec v1.10)";
|
||||
mc->init = riscv_virt_board_init;
|
||||
mc->max_cpus = 8; /* hardcoded limit in BBL */
|
||||
}
|
||||
|
||||
DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
|
||||
|
||||
static void riscv_virt_board_register_types(void)
|
||||
{
|
||||
type_register_static(&riscv_virt_board_device);
|
||||
}
|
||||
|
||||
type_init(riscv_virt_board_register_types);
|
||||
74
include/hw/riscv/virt.h
Normal file
74
include/hw/riscv/virt.h
Normal file
@ -0,0 +1,74 @@
|
||||
/*
|
||||
* SiFive VirtIO Board
|
||||
*
|
||||
* Copyright (c) 2017 SiFive, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2 or later, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef HW_VIRT_H
|
||||
#define HW_VIRT_H
|
||||
|
||||
#define TYPE_RISCV_VIRT_BOARD "riscv.virt"
|
||||
#define VIRT(obj) \
|
||||
OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD)
|
||||
|
||||
enum { ROM_BASE = 0x1000 };
|
||||
|
||||
typedef struct {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
RISCVHartArrayState soc;
|
||||
DeviceState *plic;
|
||||
void *fdt;
|
||||
int fdt_size;
|
||||
} RISCVVirtState;
|
||||
|
||||
enum {
|
||||
VIRT_DEBUG,
|
||||
VIRT_MROM,
|
||||
VIRT_TEST,
|
||||
VIRT_CLINT,
|
||||
VIRT_PLIC,
|
||||
VIRT_UART0,
|
||||
VIRT_VIRTIO,
|
||||
VIRT_DRAM
|
||||
};
|
||||
|
||||
|
||||
enum {
|
||||
UART0_IRQ = 10,
|
||||
VIRTIO_IRQ = 1, /* 1 to 8 */
|
||||
VIRTIO_COUNT = 8,
|
||||
VIRTIO_NDEV = 10
|
||||
};
|
||||
|
||||
#define VIRT_PLIC_HART_CONFIG "MS"
|
||||
#define VIRT_PLIC_NUM_SOURCES 127
|
||||
#define VIRT_PLIC_NUM_PRIORITIES 7
|
||||
#define VIRT_PLIC_PRIORITY_BASE 0x0
|
||||
#define VIRT_PLIC_PENDING_BASE 0x1000
|
||||
#define VIRT_PLIC_ENABLE_BASE 0x2000
|
||||
#define VIRT_PLIC_ENABLE_STRIDE 0x80
|
||||
#define VIRT_PLIC_CONTEXT_BASE 0x200000
|
||||
#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
|
||||
|
||||
#if defined(TARGET_RISCV32)
|
||||
#define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
|
||||
#elif defined(TARGET_RISCV64)
|
||||
#define VIRT_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user