7e5157696b
The spec defines 3 registers, even though only index 0 and 2 are valid
on POWER9. The same model is used on POWER10. Register 1 is defined
there but we currently don't use it in skiboot. So we can keep
reporting an error on write.
Reported by Coverity (CID 1487176).
Fixes:
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.. | ||
designware.h | ||
gpex.h | ||
i440fx.h | ||
mv64361.h | ||
pam.h | ||
pnv_phb3_regs.h | ||
pnv_phb3.h | ||
pnv_phb4_regs.h | ||
pnv_phb4.h | ||
ppce500.h | ||
q35.h | ||
remote.h | ||
sabre.h | ||
spapr.h | ||
uninorth.h | ||
xilinx-pcie.h |