mirror of https://gitlab.com/qemu-project/qemu
uninorth: use qdev gpios for PCI IRQs
Currently an object link property is used to pass a reference to the OpenPIC into the PCI host bridge so that pci_unin_init_irqs() can connect the PCI IRQs to the PIC itself. This can be simplified by defining the PCI IRQs as qdev gpios and then wiring up the PCI IRQs to the PIC in the New World machine init function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201013114922.2946-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This commit is contained in:
Mark Cave-Ayland
parent
b950914df3
commit
40a0deb74b
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@ -32,8 +32,6 @@
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#include "hw/pci-host/uninorth.h"
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#include "trace.h"
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static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
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static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (irq_num + (pci_dev->devfn >> 3)) & 3;
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@ -43,7 +41,7 @@ static void pci_unin_set_irq(void *opaque, int irq_num, int level)
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{
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UNINHostState *s = opaque;
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trace_unin_set_irq(unin_irq_line[irq_num], level);
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trace_unin_set_irq(irq_num, level);
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qemu_set_irq(s->irqs[irq_num], level);
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}
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@ -112,15 +110,6 @@ static const MemoryRegionOps unin_data_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void pci_unin_init_irqs(UNINHostState *s)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
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s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]);
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}
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}
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static char *pci_unin_main_ofw_unit_address(const SysBusDevice *dev)
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{
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UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
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@ -141,7 +130,6 @@ static void pci_unin_main_realize(DeviceState *dev, Error **errp)
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
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pci_unin_init_irqs(s);
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/* DEC 21154 bridge */
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#if 0
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@ -172,15 +160,12 @@ static void pci_unin_main_init(Object *obj)
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"unin-pci-hole", &s->pci_mmio,
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0x80000000ULL, 0x10000000ULL);
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object_property_add_link(obj, "pic", TYPE_OPENPIC,
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(Object **) &s->pic,
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qdev_prop_allow_set_link_before_realize,
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0);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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sysbus_init_mmio(sbd, &s->pci_hole);
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sysbus_init_mmio(sbd, &s->pci_io);
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qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
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}
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static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
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@ -196,7 +181,6 @@ static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
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pci_unin_init_irqs(s);
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}
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static void pci_u3_agp_init(Object *obj)
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@ -220,15 +204,12 @@ static void pci_u3_agp_init(Object *obj)
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"unin-pci-hole", &s->pci_mmio,
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0x80000000ULL, 0x70000000ULL);
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object_property_add_link(obj, "pic", TYPE_OPENPIC,
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(Object **) &s->pic,
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qdev_prop_allow_set_link_before_realize,
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0);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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sysbus_init_mmio(sbd, &s->pci_hole);
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sysbus_init_mmio(sbd, &s->pci_io);
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qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
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}
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static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
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@ -244,7 +225,6 @@ static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
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pci_unin_init_irqs(s);
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}
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static void pci_unin_agp_init(Object *obj)
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@ -259,13 +239,10 @@ static void pci_unin_agp_init(Object *obj)
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
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obj, "unin-agp-conf-data", 0x1000);
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object_property_add_link(obj, "pic", TYPE_OPENPIC,
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(Object **) &s->pic,
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qdev_prop_allow_set_link_before_realize,
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0);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
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}
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static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
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@ -281,7 +258,6 @@ static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
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PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
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pci_unin_init_irqs(s);
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}
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static void pci_unin_internal_init(Object *obj)
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@ -296,13 +272,10 @@ static void pci_unin_internal_init(Object *obj)
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
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obj, "unin-pci-conf-data", 0x1000);
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object_property_add_link(obj, "pic", TYPE_OPENPIC,
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(Object **) &s->pic,
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qdev_prop_allow_set_link_before_realize,
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0);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
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}
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static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
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@ -303,8 +303,6 @@ static void ppc_core99_init(MachineState *machine)
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/* 970 gets a U3 bus */
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/* Uninorth AGP bus */
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dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
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object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
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&error_abort);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
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s = SYS_BUS_DEVICE(dev);
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@ -317,32 +315,38 @@ static void ppc_core99_init(MachineState *machine)
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sysbus_mmio_map(s, 0, 0xf0800000);
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sysbus_mmio_map(s, 1, 0xf0c00000);
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for (i = 0; i < 4; i++) {
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qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
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}
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machine_arch = ARCH_MAC99_U3;
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} else {
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/* Use values found on a real PowerMac */
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/* Uninorth AGP bus */
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dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
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object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
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&error_abort);
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_mmio_map(s, 0, 0xf0800000);
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sysbus_mmio_map(s, 1, 0xf0c00000);
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for (i = 0; i < 4; i++) {
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qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
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}
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/* Uninorth internal bus */
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dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
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object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
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&error_abort);
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_mmio_map(s, 0, 0xf4800000);
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sysbus_mmio_map(s, 1, 0xf4c00000);
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for (i = 0; i < 4; i++) {
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qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
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}
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/* Uninorth main bus */
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dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
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qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000);
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object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
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&error_abort);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
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s = SYS_BUS_DEVICE(dev);
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@ -355,6 +359,10 @@ static void ppc_core99_init(MachineState *machine)
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sysbus_mmio_map(s, 0, 0xf2800000);
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sysbus_mmio_map(s, 1, 0xf2c00000);
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for (i = 0; i < 4; i++) {
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qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
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}
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machine_arch = ARCH_MAC99;
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}
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@ -26,7 +26,6 @@
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#define UNINORTH_H
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/openpic.h"
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#include "qom/object.h"
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/* UniNorth version */
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@ -51,7 +50,6 @@ struct UNINHostState {
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PCIHostState parent_obj;
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uint32_t ofw_addr;
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OpenPICState *pic;
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qemu_irq irqs[4];
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MemoryRegion pci_mmio;
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MemoryRegion pci_hole;
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