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ppc/pnv: Fix number of registers in the PCIe controller on POWER9

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The spec defines 3 registers, even though only index 0 and 2 are valid
on POWER9. The same model is used on POWER10. Register 1 is defined
there but we currently don't use it in skiboot. So we can keep
reporting an error on write.

Reported by Coverity (CID 1487176).

Fixes: 4f9924c4d4 ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge")
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220401091925.770803-1-fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Frederic Barrat 2022-04-04 08:49:06 +02:00 committed by Cédric Le Goater
parent ef95a24494
commit 7e5157696b
1 changed files with 1 additions and 1 deletions
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2
include/hw/pci-host/pnv_phb4.h
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@ -180,7 +180,7 @@ struct PnvPhb4PecState {
MemoryRegion nest_regs_mr;
/* PCI registers, excluding per-stack */
#define PHB4_PEC_PCI_REGS_COUNT 0x2
#define PHB4_PEC_PCI_REGS_COUNT 0x3
uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT];
MemoryRegion pci_regs_mr;