qemu/include/hw/intc
Peter Maydell e5cba10ee1 hw/intc/arm_gicv3: Support multiple redistributor regions
Our GICv3 QOM interface includes an array property
redist-region-count which allows board models to specify that the
registributor registers are not in a single contiguous range, but
split into multiple pieces.  We implemented this for KVM, but
currently the TCG GICv3 model insists that there is only one region.
You can see the limit being hit with a setup like:
  qemu-system-aarch64 -machine virt,gic-version=3 -smp 124

Add support for split regions to the TCG GICv3.  To do this we switch
from allocating a simple array of MemoryRegions to an array of
GICv3RedistRegion structs so that we can use the GICv3RedistRegion as
the opaque pointer in the MemoryRegion read/write callbacks.  Each
GICv3RedistRegion contains the MemoryRegion, a backpointer allowing
the read/write callback to get hold of the GICv3State, and an index
which allows us to calculate which CPU's redistributor is being
accessed.

Note that arm_gicv3_kvm always passes in NULL as the ops argument
to gicv3_init_irqs_and_mmio(), so the only MemoryRegion read/write
callbacks we need to update to handle this new scheme are the
gicv3_redist_read/write functions used by the emulated GICv3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-15 16:12:59 +00:00
..
allwinner-a10-pic.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
arm_gic_common.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
arm_gic.h Use DECLARE_*CHECKER* when possible (--force mode) 2020-09-09 09:27:11 -04:00
arm_gicv3_common.h hw/intc/arm_gicv3: Support multiple redistributor regions 2021-11-15 16:12:59 +00:00
arm_gicv3_its_common.h hw/intc: GICv3 ITS register definitions added 2021-09-13 16:07:54 +01:00
arm_gicv3.h Use DECLARE_*CHECKER* when possible (--force mode) 2020-09-09 09:27:11 -04:00
armv7m_nvic.h arm: Move system PPB container handling to armv7m 2021-09-01 11:08:18 +01:00
aspeed_vic.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
bcm2835_ic.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
bcm2836_control.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
goldfish_pic.h hw/m68k: Fix typo in SPDX tag 2021-11-09 10:11:27 +01:00
heathrow_pic.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
i8259.h hw: replace hw/i386/pc.h with a header just for the i8259 2019-12-17 19:33:49 +01:00
ibex_plic.h hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines 2021-09-21 07:56:49 +10:00
imx_avic.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
imx_gpcv2.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
intc.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
loongson_liointc.h hw/intc: Rework Loongson LIOINTC 2021-01-04 23:24:44 +01:00
m68k_irqc.h hw/m68k: Fix typo in SPDX tag 2021-11-09 10:11:27 +01:00
mips_gic.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
ppc-uic.h hw/ppc: Remove unused ppcuic_init() 2021-01-19 10:20:29 +11:00
realview_gic.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
riscv_aclint.h hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT 2021-09-21 07:56:49 +10:00
rx_icu.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
sifive_plic.h hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines 2021-09-21 07:56:49 +10:00
xlnx-pmu-iomod-intc.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
xlnx-zynqmp-ipi.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00