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hw/intc/arm_gicv3: Support multiple redistributor regions

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Our GICv3 QOM interface includes an array property
redist-region-count which allows board models to specify that the
registributor registers are not in a single contiguous range, but
split into multiple pieces.  We implemented this for KVM, but
currently the TCG GICv3 model insists that there is only one region.
You can see the limit being hit with a setup like:
  qemu-system-aarch64 -machine virt,gic-version=3 -smp 124

Add support for split regions to the TCG GICv3.  To do this we switch
from allocating a simple array of MemoryRegions to an array of
GICv3RedistRegion structs so that we can use the GICv3RedistRegion as
the opaque pointer in the MemoryRegion read/write callbacks.  Each
GICv3RedistRegion contains the MemoryRegion, a backpointer allowing
the read/write callback to get hold of the GICv3State, and an index
which allows us to calculate which CPU's redistributor is being
accessed.

Note that arm_gicv3_kvm always passes in NULL as the ops argument
to gicv3_init_irqs_and_mmio(), so the only MemoryRegion read/write
callbacks we need to update to handle this new scheme are the
gicv3_redist_read/write functions used by the emulated GICv3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell 2021-09-30 16:08:42 +01:00
parent 046164155a
commit e5cba10ee1
5 changed files with 46 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
hw/intc/arm_gicv3.c
View File

@ -387,12 +387,6 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
return;
}
if (s->nb_redist_regions != 1) {
error_setg(errp, "VGICv3 redist region number(%d) not equal to 1",
s->nb_redist_regions);
return;
}
gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
gicv3_init_cpuif(s);

15
hw/intc/arm_gicv3_common.c
View File

@ -254,6 +254,7 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
{
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
int i;
int cpuidx;
/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
* GPIO array layout is thus:
@ -282,14 +283,20 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
"gicv3_dist", 0x10000);
sysbus_init_mmio(sbd, &s->iomem_dist);
s->iomem_redist = g_new0(MemoryRegion, s->nb_redist_regions);
s->redist_regions = g_new0(GICv3RedistRegion, s->nb_redist_regions);
cpuidx = 0;
for (i = 0; i < s->nb_redist_regions; i++) {
char *name = g_strdup_printf("gicv3_redist_region[%d]", i);
GICv3RedistRegion *region = &s->redist_regions[i];
memory_region_init_io(&s->iomem_redist[i], OBJECT(s),
ops ? &ops[1] : NULL, s, name,
region->gic = s;
region->cpuidx = cpuidx;
cpuidx += s->redist_region_count[i];
memory_region_init_io(&region->iomem, OBJECT(s),
ops ? &ops[1] : NULL, region, name,
s->redist_region_count[i] * GICV3_REDIST_SIZE);
sysbus_init_mmio(sbd, &s->iomem_redist[i]);
sysbus_init_mmio(sbd, &region->iomem);
g_free(name);
}
}

4
hw/intc/arm_gicv3_kvm.c
View File

@ -825,7 +825,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
if (!multiple_redist_region_allowed) {
kvm_arm_register_device(&s->iomem_redist[0], -1,
kvm_arm_register_device(&s->redist_regions[0].iomem, -1,
KVM_DEV_ARM_VGIC_GRP_ADDR,
KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
} else {
@ -838,7 +838,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
uint64_t addr_ormask =
i | ((uint64_t)s->redist_region_count[i] << 52);
kvm_arm_register_device(&s->iomem_redist[i], -1,
kvm_arm_register_device(&s->redist_regions[i].iomem, -1,
KVM_DEV_ARM_VGIC_GRP_ADDR,
KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION,
s->dev_fd, addr_ormask);

40
hw/intc/arm_gicv3_redist.c
View File

@ -425,22 +425,24 @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset,
MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
GICv3State *s = opaque;
GICv3RedistRegion *region = opaque;
GICv3State *s = region->gic;
GICv3CPUState *cs;
MemTxResult r;
int cpuidx;
assert((offset & (size - 1)) == 0);
/* This region covers all the redistributor pages; there are
* (for GICv3) two 64K pages per CPU. At the moment they are
* all contiguous (ie in this one region), though we might later
* want to allow splitting of redistributor pages into several
* blocks so we can support more CPUs.
/*
* There are (for GICv3) two 64K redistributor pages per CPU.
* In some cases the redistributor pages for all CPUs are not
* contiguous (eg on the virt board they are split into two
* parts if there are too many CPUs to all fit in the same place
* in the memory map); if so then the GIC has multiple MemoryRegions
* for the redistributors.
*/
cpuidx = offset / 0x20000;
offset %= 0x20000;
assert(cpuidx < s->num_cpu);
cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;
offset %= GICV3_REDIST_SIZE;
cs = &s->cpu[cpuidx];
@ -482,22 +484,24 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size, MemTxAttrs attrs)
{
GICv3State *s = opaque;
GICv3RedistRegion *region = opaque;
GICv3State *s = region->gic;
GICv3CPUState *cs;
MemTxResult r;
int cpuidx;
assert((offset & (size - 1)) == 0);
/* This region covers all the redistributor pages; there are
* (for GICv3) two 64K pages per CPU. At the moment they are
* all contiguous (ie in this one region), though we might later
* want to allow splitting of redistributor pages into several
* blocks so we can support more CPUs.
/*
* There are (for GICv3) two 64K redistributor pages per CPU.
* In some cases the redistributor pages for all CPUs are not
* contiguous (eg on the virt board they are split into two
* parts if there are too many CPUs to all fit in the same place
* in the memory map); if so then the GIC has multiple MemoryRegions
* for the redistributors.
*/
cpuidx = offset / 0x20000;
offset %= 0x20000;
assert(cpuidx < s->num_cpu);
cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;
offset %= GICV3_REDIST_SIZE;
cs = &s->cpu[cpuidx];

12
include/hw/intc/arm_gicv3_common.h
View File

@ -215,13 +215,23 @@ struct GICv3CPUState {
bool seenbetter;
};
/*
* The redistributor pages might be split into more than one region
* on some machine types if there are many CPUs.
*/
typedef struct GICv3RedistRegion {
GICv3State *gic;
MemoryRegion iomem;
uint32_t cpuidx; /* index of first CPU this region covers */
} GICv3RedistRegion;
struct GICv3State {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem_dist; /* Distributor */
MemoryRegion *iomem_redist; /* Redistributor Regions */
GICv3RedistRegion *redist_regions; /* Redistributor Regions */
uint32_t *redist_region_count; /* redistributor count within each region */
uint32_t nb_redist_regions; /* number of redist regions */