qemu/target/riscv
Daniel Henrique Barboza 92becce5e1 target/riscv: add KVM specific MISA properties
Using all TCG user properties in KVM is tricky. First because KVM
supports only a small subset of what TCG provides, so most of the
cpu->cfg flags do nothing for KVM.

Second, and more important, we don't have a way of telling if any given
value is an user input or not. For TCG this has a small impact since we
just validating everything and error out if needed. But for KVM it would
be good to know if a given value was set by the user or if it's a value
already provided by KVM. Otherwise we don't know how to handle failed
kvm_set_one_regs() when writing the configurations back.

These characteristics make it overly complicated to use the same user
facing flags for both KVM and TCG. A simpler approach is to create KVM
specific properties that have specialized logic, forking KVM and TCG use
cases for those cases only. Fully separating KVM/TCG properties is
unneeded at this point - in fact we want the user experience to be as
equal as possible, regardless of the acceleration chosen.

We'll start this fork with the MISA properties, adding the MISA bits
that the KVM driver currently supports. A new KVMCPUConfig type is
introduced. It'll hold general information about an extension. For MISA
extensions we're going to use the newly created getters of
misa_ext_infos[] to populate their name and description. 'offset' holds
the MISA bit (RVA, RVC, ...). We're calling it 'offset' instead of
'misa_bit' because this same KVMCPUConfig struct will be used to
multi-letter extensions later on.

This new type also holds a 'user_set' flag. This flag will be set when
the user set an option that's different than what is already configured
in the host, requiring KVM intervention to write the regs back during
kvm_arch_init_vcpu(). Similar mechanics will be implemented for
multi-letter extensions as well.

There is no need to duplicate more code than necessary, so we're going
to use the existing kvm_riscv_init_user_properties() to add the KVM
specific properties. Any code that is adding a TCG user prop is then
changed slightly to verify first if there's a KVM prop with the same
name already added.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10 22:29:20 +10:00
..
insn_trans target/riscv: Add support for Zvfbfwma extension 2023-07-10 22:29:15 +10:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu_bits.h riscv: Make sure an exception is raised if a pte is malformed 2023-05-05 10:49:50 +10:00
cpu_cfg.h target/riscv: Add properties for BF16 extensions 2023-07-10 22:29:15 +10:00
cpu_helper.c target/riscv: Set the correct exception for implict G-stage translation fail 2023-07-10 22:29:15 +10:00
cpu_user.h
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu-param.h target/riscv: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu-qom.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu.c target/riscv: add KVM specific MISA properties 2023-07-10 22:29:20 +10:00
cpu.h target/riscv/cpu: add misa_ext_info_arr[] 2023-07-10 22:29:20 +10:00
crypto_helper.c target/riscv: Use aesdec_ISB_ISR_IMC_AK 2023-07-09 13:47:17 +01:00
csr.c target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV 2023-07-10 22:29:14 +10:00
debug.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
debug.h target/riscv: Add itrigger support when icount is enabled 2023-01-06 10:42:55 +10:00
fpu_helper.c target/riscv: Add support for Zfbfmin extension 2023-07-10 22:29:15 +10:00
gdbstub.c target/riscv: Use PRV_RESERVED instead of PRV_H 2023-05-05 10:49:50 +10:00
helper.h target/riscv: Add support for Zvfbfwma extension 2023-07-10 22:29:15 +10:00
insn16.decode target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn32.decode target/riscv: Add support for Zvfbfwma extension 2023-07-10 22:29:15 +10:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: Introduce mmuidx_2stage 2023-05-05 10:49:50 +10:00
Kconfig
kvm_riscv.h target/riscv: use KVM scratch CPUs to init KVM properties 2023-07-10 22:29:15 +10:00
kvm-stub.c
kvm.c target/riscv: add KVM specific MISA properties 2023-07-10 22:29:20 +10:00
m128_helper.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
machine.c target/riscv: Restrict KVM-specific fields from ArchCPU 2023-06-28 14:27:59 +02:00
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
monitor.c target/riscv: remove RISCV_FEATURE_MMU 2023-03-01 13:47:15 -08:00
op_helper.c target/riscv: Make MPV only work when MPP != PRV_M 2023-07-10 22:29:14 +10:00
pmp.c target/riscv: Smepmp: Return error when access permission not allowed in PMP 2023-06-13 17:45:30 +10:00
pmp.h target/riscv: Change the return type of pmp_hart_has_privs() to bool 2023-06-13 17:09:13 +10:00
pmu.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
pmu.h riscv: Clean up includes 2023-02-08 07:28:05 +01:00
riscv-qmp-cmds.c target/riscv: add TYPE_RISCV_DYNAMIC_CPU 2023-05-05 10:49:50 +10:00
sbi_ecall_interface.h target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
time_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events
trace.h
translate.c target/riscv: Add support for Zfbfmin extension 2023-07-10 22:29:15 +10:00
vector_helper.c target/riscv: Add support for Zvfbfwma extension 2023-07-10 22:29:15 +10:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00