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qemu/target/riscv
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Hiroaki Yamamoto 6979b7b3f2 target/riscv: Fix privilege mode of G-stage translation for debugging 
G-stage translation should be considered to be user-level access in
riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill().

This fixes a bug that prevents gdb from reading memory while the VM is
running in VS-mode.

Signed-off-by: Hiroaki Yamamoto <hrak1529@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240228081028.35081-1-hrak1529@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-08 20:48:03 +10:00
..
insn_trans trans_rvv.c.inc: remove 'is_store' bool from load/store fns 2024-03-08 20:48:03 +10:00
kvm target/riscv/kvm: update KVM exts to Linux 6.8 2024-03-08 20:48:03 +10:00
tcg target/riscv: Promote svade to a normal extension 2024-03-08 16:35:28 +10:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu_bits.h target/riscv: FCSR doesn't contain vxrm and vxsat 2024-02-09 20:43:14 +10:00
cpu_cfg.h RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
cpu_helper.c target/riscv: Fix privilege mode of G-stage translation for debugging 2024-03-08 20:48:03 +10:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu-param.h target/riscv: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu-qom.h target/riscv: add rv32i, rv32e and rv64e CPUs 2024-02-09 20:49:41 +10:00
cpu.c target/riscv: move ratified/frozen exts to non-experimental 2024-03-08 20:48:03 +10:00
cpu.h target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit 2024-03-08 20:48:03 +10:00
crypto_helper.c target/riscv: Use accelerated helper for AES64KS1I 2023-09-11 11:45:55 +10:00
csr.c target/riscv: UPDATE xATP write CSR 2024-03-08 16:38:09 +10:00
debug.c target/riscv: Implement optional CSR mcontext of debug Sdtrig extension 2024-02-09 20:40:32 +10:00
debug.h target/riscv: Allocate itrigger timers only once 2023-09-11 11:45:55 +10:00
fpu_helper.c riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
gdbstub.c gdbstub: Add members to identify registers to GDBFeature 2024-02-28 09:10:11 +00:00
helper.h target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
insn16.decode target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn32.decode target/riscv: Add support for Zacas extension 2024-01-10 18:47:47 +10:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: Use env_archcpu() in [check_]nanbox() 2023-11-07 12:13:27 +01:00
Kconfig kconfig: use "select" to enable semihosting 2024-02-09 17:52:30 +00:00
m128_helper.c target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
machine.c target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit 2024-03-08 20:48:03 +10:00
meson.build target/riscv: move KVM only files to kvm subdir 2023-10-12 12:20:24 +10:00
monitor.c riscv: spelling fixes 2023-09-08 13:08:52 +03:00
op_helper.c target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index 2024-02-03 16:46:10 +10:00
pmp.c target/riscv: pmp: Ignore writes when RW=01 and MML=0 2024-01-10 18:47:47 +10:00
pmp.h target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 2024-01-10 18:47:46 +10:00
pmu.c target/riscv: Add "pmu-mask" property to replace "pmu-num" 2023-11-07 11:06:02 +10:00
pmu.h target/riscv: Add missing include guard in pmu.h 2024-03-08 16:39:32 +10:00
riscv-qmp-cmds.c riscv-qmp-cmds.c: add profile flags in cpu-model-expansion 2024-01-10 18:47:47 +10:00
sbi_ecall_interface.h target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
time_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
vcrypto_helper.c target/riscv: Add Zvksed ISA extension support 2023-09-11 11:45:55 +10:00
vector_helper.c target/riscv: Fix shift count overflow 2024-03-08 20:48:03 +10:00
vector_internals.c riscv: Clean up includes 2024-01-30 21:20:20 +03:00
vector_internals.h riscv: Clean up includes 2024-01-30 21:20:20 +03:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00