qemu/target/riscv
Atish Patra 7100fe6c24 target/riscv: Enable privileged spec version 1.12
Virt machine uses privileged specification version 1.12 now.
All other machine continue to use the default one defined for that
machine unless changed to 1.12 by the user explicitly.

This commit enforces the privilege version for csrs introduced in
v1.12 or after.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-7-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-22 10:35:16 +10:00
..
insn_trans Replace config-time define HOST_WORDS_BIGENDIAN 2022-04-06 10:50:37 +02:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: Add rev8 instruction, removing grev/grevi 2021-10-07 08:41:33 +10:00
cpu_bits.h target/riscv: Add *envcfg* CSRs support 2022-04-22 10:35:16 +10:00
cpu_helper.c target/riscv: hardwire mstatus.FS to zero when enable zfinx 2022-03-03 13:14:50 +10:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu-param.h target/riscv: Add a virtualised MMU Mode 2020-11-09 15:08:45 -08:00
cpu.c target/riscv: Enable privileged spec version 1.12 2022-04-22 10:35:16 +10:00
cpu.h target/riscv: Add *envcfg* CSRs support 2022-04-22 10:35:16 +10:00
csr.c target/riscv: Enable privileged spec version 1.12 2022-04-22 10:35:16 +10:00
fpu_helper.c target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
gdbstub.c target/riscv: correct "code should not be reached" for x-rv128 2022-02-16 12:24:18 +10:00
helper.h target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
insn16.decode target/riscv: accessors to registers upper part and 128-bit load/store 2022-01-08 15:46:10 +10:00
insn32.decode target/riscv: add support for svinval extension 2022-02-16 12:25:52 +10:00
instmap.h target/riscv: progressively load the instruction during decode 2020-02-25 20:20:23 +00:00
internals.h target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm_riscv.h target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm-stub.c target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm.c Remove qemu-common.h include from most units 2022-04-06 14:31:55 +02:00
m128_helper.c target/riscv: support for 128-bit M extension 2022-01-08 15:46:10 +10:00
machine.c target/riscv: Add *envcfg* CSRs support 2022-04-22 10:35:16 +10:00
meson.build target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
monitor.c target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl 2021-10-22 07:47:51 +10:00
op_helper.c compiler.h: replace QEMU_NORETURN with G_NORETURN 2022-04-21 17:03:51 +04:00
pmp.c target/riscv: Adjust pmpcfg access with mxl 2022-01-21 15:52:57 +10:00
pmp.h target: Include missing 'cpu.h' 2022-03-06 13:15:42 +01:00
sbi_ecall_interface.h target/riscv: Handle KVM_EXIT_RISCV_SBI exit 2022-01-21 15:52:56 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c exec/translator: Pass the locked filepointer to disas_log hook 2022-04-20 10:51:11 -07:00
vector_helper.c Replace config-time define HOST_WORDS_BIGENDIAN 2022-04-06 10:50:37 +02:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00