29a9ec9bd8
The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220303185440.512391-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
684 lines
20 KiB
C
684 lines
20 KiB
C
/*
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* QEMU RISC-V CPU
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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#include "hw/core/cpu.h"
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#include "hw/registerfields.h"
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#include "exec/cpu-defs.h"
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#include "qemu/cpu-float.h"
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#include "qom/object.h"
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#include "qemu/int128.h"
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#include "cpu_bits.h"
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#define TCG_GUEST_DEFAULT_MO 0
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#define TYPE_RISCV_CPU "riscv-cpu"
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#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
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#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
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#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
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#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
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#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
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#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
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#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
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#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
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#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
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#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
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#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
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#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
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#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
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#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
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#if defined(TARGET_RISCV32)
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# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
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#elif defined(TARGET_RISCV64)
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# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
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#endif
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#define RV(x) ((target_ulong)1 << (x - 'A'))
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#define RVI RV('I')
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#define RVE RV('E') /* E and I are mutually exclusive */
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#define RVM RV('M')
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#define RVA RV('A')
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#define RVF RV('F')
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#define RVD RV('D')
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#define RVV RV('V')
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#define RVC RV('C')
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#define RVS RV('S')
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#define RVU RV('U')
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#define RVH RV('H')
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#define RVJ RV('J')
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/* S extension denotes that Supervisor mode exists, however it is possible
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to have a core that support S mode but does not have an MMU and there
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is currently no bit in misa to indicate whether an MMU exists or not
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so a cpu features bitfield is required, likewise for optional PMP support */
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enum {
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RISCV_FEATURE_MMU,
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RISCV_FEATURE_PMP,
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RISCV_FEATURE_EPMP,
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RISCV_FEATURE_MISA,
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RISCV_FEATURE_AIA
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};
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/* Privileged specification version */
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enum {
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PRIV_VERSION_1_10_0 = 0,
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PRIV_VERSION_1_11_0,
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PRIV_VERSION_1_12_0,
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};
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#define VEXT_VERSION_1_00_0 0x00010000
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enum {
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TRANSLATE_SUCCESS,
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TRANSLATE_FAIL,
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TRANSLATE_PMP_FAIL,
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TRANSLATE_G_STAGE_FAIL
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};
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#define MMU_USER_IDX 3
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#define MAX_RISCV_PMPS (16)
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typedef struct CPUArchState CPURISCVState;
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#if !defined(CONFIG_USER_ONLY)
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#include "pmp.h"
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#endif
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#define RV_VLEN_MAX 1024
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FIELD(VTYPE, VLMUL, 0, 3)
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FIELD(VTYPE, VSEW, 3, 3)
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FIELD(VTYPE, VTA, 6, 1)
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FIELD(VTYPE, VMA, 7, 1)
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FIELD(VTYPE, VEDIV, 8, 2)
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FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
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struct CPUArchState {
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target_ulong gpr[32];
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target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
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uint64_t fpr[32]; /* assume both F and D extensions */
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/* vector coprocessor state. */
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uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
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target_ulong vxrm;
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target_ulong vxsat;
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target_ulong vl;
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target_ulong vstart;
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target_ulong vtype;
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bool vill;
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target_ulong pc;
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target_ulong load_res;
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target_ulong load_val;
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target_ulong frm;
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target_ulong badaddr;
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uint32_t bins;
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target_ulong guest_phys_fault_addr;
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target_ulong priv_ver;
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target_ulong bext_ver;
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target_ulong vext_ver;
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/* RISCVMXL, but uint32_t for vmstate migration */
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uint32_t misa_mxl; /* current mxl */
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uint32_t misa_mxl_max; /* max mxl for this cpu */
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uint32_t misa_ext; /* current extensions */
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uint32_t misa_ext_mask; /* max ext for this cpu */
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uint32_t xl; /* current xlen */
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/* 128-bit helpers upper part return value */
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target_ulong retxh;
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uint32_t features;
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#ifdef CONFIG_USER_ONLY
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uint32_t elf_flags;
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#endif
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#ifndef CONFIG_USER_ONLY
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target_ulong priv;
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/* This contains QEMU specific information about the virt state. */
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target_ulong virt;
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target_ulong geilen;
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target_ulong resetvec;
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target_ulong mhartid;
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/*
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* For RV32 this is 32-bit mstatus and 32-bit mstatush.
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* For RV64 this is a 64-bit mstatus.
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*/
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uint64_t mstatus;
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uint64_t mip;
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uint64_t miclaim;
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uint64_t mie;
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uint64_t mideleg;
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target_ulong satp; /* since: priv-1.10.0 */
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target_ulong stval;
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target_ulong medeleg;
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target_ulong stvec;
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target_ulong sepc;
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target_ulong scause;
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target_ulong mtvec;
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target_ulong mepc;
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target_ulong mcause;
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target_ulong mtval; /* since: priv-1.10.0 */
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/* Machine and Supervisor interrupt priorities */
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uint8_t miprio[64];
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uint8_t siprio[64];
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/* AIA CSRs */
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target_ulong miselect;
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target_ulong siselect;
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/* Hypervisor CSRs */
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target_ulong hstatus;
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target_ulong hedeleg;
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uint64_t hideleg;
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target_ulong hcounteren;
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target_ulong htval;
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target_ulong htinst;
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target_ulong hgatp;
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target_ulong hgeie;
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target_ulong hgeip;
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uint64_t htimedelta;
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/* Hypervisor controlled virtual interrupt priorities */
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target_ulong hvictl;
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uint8_t hviprio[64];
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/* Upper 64-bits of 128-bit CSRs */
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uint64_t mscratchh;
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uint64_t sscratchh;
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/* Virtual CSRs */
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/*
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* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
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* For RV64 this is a 64-bit vsstatus.
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*/
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uint64_t vsstatus;
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target_ulong vstvec;
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target_ulong vsscratch;
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target_ulong vsepc;
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target_ulong vscause;
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target_ulong vstval;
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target_ulong vsatp;
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/* AIA VS-mode CSRs */
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target_ulong vsiselect;
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target_ulong mtval2;
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target_ulong mtinst;
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/* HS Backup CSRs */
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target_ulong stvec_hs;
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target_ulong sscratch_hs;
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target_ulong sepc_hs;
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target_ulong scause_hs;
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target_ulong stval_hs;
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target_ulong satp_hs;
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uint64_t mstatus_hs;
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/* Signals whether the current exception occurred with two-stage address
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translation active. */
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bool two_stage_lookup;
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target_ulong scounteren;
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target_ulong mcounteren;
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target_ulong sscratch;
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target_ulong mscratch;
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/* temporary htif regs */
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uint64_t mfromhost;
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uint64_t mtohost;
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uint64_t timecmp;
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/* physical memory protection */
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pmp_table_t pmp_state;
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target_ulong mseccfg;
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/* machine specific rdtime callback */
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uint64_t (*rdtime_fn)(uint32_t);
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uint32_t rdtime_fn_arg;
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/* machine specific AIA ireg read-modify-write callback */
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#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
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((((__xlen) & 0xff) << 24) | \
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(((__vgein) & 0x3f) << 20) | \
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(((__virt) & 0x1) << 18) | \
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(((__priv) & 0x3) << 16) | \
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(__isel & 0xffff))
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#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
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#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
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#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1)
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#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f)
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#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff)
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int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
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target_ulong *val, target_ulong new_val, target_ulong write_mask);
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void *aia_ireg_rmw_fn_arg[4];
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/* True if in debugger mode. */
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bool debugger;
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/*
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* CSRs for PointerMasking extension
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*/
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target_ulong mmte;
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target_ulong mpmmask;
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target_ulong mpmbase;
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target_ulong spmmask;
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target_ulong spmbase;
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target_ulong upmmask;
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target_ulong upmbase;
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/* CSRs for execution enviornment configuration */
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uint64_t menvcfg;
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target_ulong senvcfg;
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uint64_t henvcfg;
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#endif
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target_ulong cur_pmmask;
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target_ulong cur_pmbase;
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float_status fp_status;
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/* Fields from here on are preserved across CPU reset. */
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QEMUTimer *timer; /* Internal timer */
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hwaddr kernel_addr;
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hwaddr fdt_addr;
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/* kvm timer */
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bool kvm_timer_dirty;
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uint64_t kvm_timer_time;
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uint64_t kvm_timer_compare;
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uint64_t kvm_timer_state;
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uint64_t kvm_timer_frequency;
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};
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OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
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/**
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* RISCVCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A RISCV CPU model.
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*/
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struct RISCVCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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};
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struct RISCVCPUConfig {
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bool ext_i;
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bool ext_e;
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bool ext_g;
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bool ext_m;
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bool ext_a;
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bool ext_f;
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bool ext_d;
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bool ext_c;
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bool ext_s;
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bool ext_u;
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bool ext_h;
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bool ext_j;
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bool ext_v;
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bool ext_zba;
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bool ext_zbb;
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bool ext_zbc;
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bool ext_zbs;
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bool ext_counters;
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bool ext_ifencei;
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bool ext_icsr;
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bool ext_svinval;
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bool ext_svnapot;
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bool ext_svpbmt;
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bool ext_zdinx;
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bool ext_zfh;
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bool ext_zfhmin;
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bool ext_zfinx;
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bool ext_zhinx;
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bool ext_zhinxmin;
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bool ext_zve32f;
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bool ext_zve64f;
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/* Vendor-specific custom extensions */
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bool ext_XVentanaCondOps;
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char *priv_spec;
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char *user_spec;
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char *bext_spec;
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char *vext_spec;
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uint16_t vlen;
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uint16_t elen;
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bool mmu;
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bool pmp;
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bool epmp;
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bool aia;
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uint64_t resetvec;
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};
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typedef struct RISCVCPUConfig RISCVCPUConfig;
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/**
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* RISCVCPU:
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* @env: #CPURISCVState
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*
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* A RISCV CPU.
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*/
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struct ArchCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPURISCVState env;
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char *dyn_csr_xml;
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char *dyn_vreg_xml;
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/* Configuration Settings */
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RISCVCPUConfig cfg;
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};
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static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
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{
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return (env->misa_ext & ext) != 0;
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}
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static inline bool riscv_feature(CPURISCVState *env, int feature)
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{
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return env->features & (1ULL << feature);
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}
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static inline void riscv_set_feature(CPURISCVState *env, int feature)
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{
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env->features |= (1ULL << feature);
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}
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#include "cpu_user.h"
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extern const char * const riscv_int_regnames[];
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extern const char * const riscv_int_regnamesh[];
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extern const char * const riscv_fpr_regnames[];
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const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
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void riscv_cpu_do_interrupt(CPUState *cpu);
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int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
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int cpuid, void *opaque);
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int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
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int cpuid, void *opaque);
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int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
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uint8_t riscv_cpu_default_priority(int irq);
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int riscv_cpu_mirq_pending(CPURISCVState *env);
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int riscv_cpu_sirq_pending(CPURISCVState *env);
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int riscv_cpu_vsirq_pending(CPURISCVState *env);
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bool riscv_cpu_fp_enabled(CPURISCVState *env);
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target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
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void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
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bool riscv_cpu_vector_enabled(CPURISCVState *env);
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bool riscv_cpu_virt_enabled(CPURISCVState *env);
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void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
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bool riscv_cpu_two_stage_lookup(int mmu_idx);
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int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
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hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr);
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bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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char *riscv_isa_string(RISCVCPU *cpu);
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void riscv_cpu_list(void);
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#define cpu_list riscv_cpu_list
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#define cpu_mmu_index riscv_cpu_mmu_index
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#ifndef CONFIG_USER_ONLY
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bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
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void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
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int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
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uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
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#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
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void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
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uint32_t arg);
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void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
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int (*rmw_fn)(void *arg,
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target_ulong reg,
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target_ulong *val,
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target_ulong new_val,
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target_ulong write_mask),
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void *rmw_fn_arg);
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#endif
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void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
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void riscv_translate_init(void);
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G_NORETURN void riscv_raise_exception(CPURISCVState *env,
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uint32_t exception, uintptr_t pc);
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|
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target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
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void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
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#define TB_FLAGS_PRIV_MMU_MASK 3
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#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
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#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
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#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
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#include "exec/cpu-all.h"
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FIELD(TB_FLAGS, MEM_IDX, 0, 3)
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FIELD(TB_FLAGS, LMUL, 3, 3)
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FIELD(TB_FLAGS, SEW, 6, 3)
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/* Skip MSTATUS_VS (0x600) bits */
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FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
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FIELD(TB_FLAGS, VILL, 12, 1)
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/* Skip MSTATUS_FS (0x6000) bits */
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/* Is a Hypervisor instruction load/store allowed? */
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FIELD(TB_FLAGS, HLSX, 15, 1)
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FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
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FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
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/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
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FIELD(TB_FLAGS, XL, 20, 2)
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/* If PointerMasking should be applied */
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FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
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FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
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|
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#ifdef TARGET_RISCV32
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#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
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#else
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static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
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|
{
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|
return env->misa_mxl;
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}
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#endif
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#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
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|
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#if defined(TARGET_RISCV32)
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#define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
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|
#else
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static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
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|
{
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|
RISCVMXL xl = env->misa_mxl;
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#if !defined(CONFIG_USER_ONLY)
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/*
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* When emulating a 32-bit-only cpu, use RV32.
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* When emulating a 64-bit cpu, and MXL has been reduced to RV32,
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* MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
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|
* back to RV64 for lower privs.
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|
*/
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if (xl != MXL_RV32) {
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switch (env->priv) {
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case PRV_M:
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|
break;
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case PRV_U:
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xl = get_field(env->mstatus, MSTATUS64_UXL);
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break;
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default: /* PRV_S | PRV_H */
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xl = get_field(env->mstatus, MSTATUS64_SXL);
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|
break;
|
|
}
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|
}
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|
#endif
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|
return xl;
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|
}
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|
#endif
|
|
|
|
static inline int riscv_cpu_xlen(CPURISCVState *env)
|
|
{
|
|
return 16 << env->xl;
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|
}
|
|
|
|
#ifdef TARGET_RISCV32
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|
#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
|
|
#else
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|
static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
|
|
{
|
|
#ifdef CONFIG_USER_ONLY
|
|
return env->misa_mxl;
|
|
#else
|
|
return get_field(env->mstatus, MSTATUS64_SXL);
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Encode LMUL to lmul as follows:
|
|
* LMUL vlmul lmul
|
|
* 1 000 0
|
|
* 2 001 1
|
|
* 4 010 2
|
|
* 8 011 3
|
|
* - 100 -
|
|
* 1/8 101 -3
|
|
* 1/4 110 -2
|
|
* 1/2 111 -1
|
|
*
|
|
* then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
|
|
* e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
|
|
* => VLMAX = vlen >> (1 + 3 - (-3))
|
|
* = 256 >> 7
|
|
* = 2
|
|
*/
|
|
static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
|
|
{
|
|
uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
|
|
int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
|
|
return cpu->cfg.vlen >> (sew + 3 - lmul);
|
|
}
|
|
|
|
void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
|
|
target_ulong *cs_base, uint32_t *pflags);
|
|
|
|
void riscv_cpu_update_mask(CPURISCVState *env);
|
|
|
|
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
|
|
target_ulong *ret_value,
|
|
target_ulong new_value, target_ulong write_mask);
|
|
RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
|
|
target_ulong *ret_value,
|
|
target_ulong new_value,
|
|
target_ulong write_mask);
|
|
|
|
static inline void riscv_csr_write(CPURISCVState *env, int csrno,
|
|
target_ulong val)
|
|
{
|
|
riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
|
|
}
|
|
|
|
static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
|
|
{
|
|
target_ulong val = 0;
|
|
riscv_csrrw(env, csrno, &val, 0, 0);
|
|
return val;
|
|
}
|
|
|
|
typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
|
|
int csrno);
|
|
typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
|
|
target_ulong *ret_value);
|
|
typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
|
|
target_ulong new_value);
|
|
typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
|
|
target_ulong *ret_value,
|
|
target_ulong new_value,
|
|
target_ulong write_mask);
|
|
|
|
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
|
|
Int128 *ret_value,
|
|
Int128 new_value, Int128 write_mask);
|
|
|
|
typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
|
|
Int128 *ret_value);
|
|
typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
|
|
Int128 new_value);
|
|
|
|
typedef struct {
|
|
const char *name;
|
|
riscv_csr_predicate_fn predicate;
|
|
riscv_csr_read_fn read;
|
|
riscv_csr_write_fn write;
|
|
riscv_csr_op_fn op;
|
|
riscv_csr_read128_fn read128;
|
|
riscv_csr_write128_fn write128;
|
|
/* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
|
|
uint32_t min_priv_ver;
|
|
} riscv_csr_operations;
|
|
|
|
/* CSR function table constants */
|
|
enum {
|
|
CSR_TABLE_SIZE = 0x1000
|
|
};
|
|
|
|
/* CSR function table */
|
|
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
|
|
|
|
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
|
|
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
|
|
|
|
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
|
|
|
|
#endif /* RISCV_CPU_H */
|