qemu/target/ppc/translate
Víctor Colombo 205eb5a89e target/ppc: Change VSX instructions behavior to fill with zeros
ISA v3.1 changed some VSX instructions behavior by changing what the
other words/doubleword in the result should contain when the result is
only one word/doubleword. e.g. xsmaxdp operates on doubleword 0 and
saves the result also in doubleword 0.
Before, the second doubleword result was undefined according to the
ISA, but now it's stated that it should be zeroed.

Even tough the result was undefined before, hardware implementing these
instructions already filled these fields with 0s. Changing every ISA
version in QEMU to this behavior makes the results match what happens
in hardware.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220204181944.65063-1-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09 09:08:56 +01:00
..
branch-impl.c.inc PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
dfp-impl.c.inc target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree 2021-11-09 10:32:52 +11:00
fixedpoint-impl.c.inc exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
fp-impl.c.inc target/ppc: Remove PowerPC 601 CPUs 2022-02-09 09:08:55 +01:00
fp-ops.c.inc target/ppc: Move load and store floating point instructions to decodetree 2021-11-09 10:32:51 +11:00
spe-impl.c.inc ppc patch queue 2020-08-18 2020-08-24 09:35:21 +01:00
spe-ops.c.inc meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00
vmx-impl.c.inc target/ppc: Implement Vector Mask Move insns 2021-12-17 17:57:13 +01:00
vmx-ops.c.inc target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree 2021-11-09 10:32:52 +11:00
vsx-impl.c.inc target/ppc: Change VSX instructions behavior to fill with zeros 2022-02-09 09:08:56 +01:00
vsx-ops.c.inc target/ppc: move xscvqpdp to decodetree 2021-12-17 17:57:18 +01:00