qemu/hw/i2c
Jamin Lin be8c15118a hw/i2c/aspeed: Add support for 64 bit addresses
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 00000000" which
is 64bits address.

The AST2700 support the maximum DRAM size is 8 GB.
The DRAM physical address range is from "0x4_0000_0000" to
"0x5_FFFF_FFFF".

The DRAM offset range is from "0x0_0000_0000" to
"0x1_FFFF_FFFF" and it is enough to use bits [33:0]
saving the dram offset.

Therefore, save the high part physical address bit[1:0]
of Tx/Rx buffer address as dma_dram_offset bit[33:32].
It does not need to decrease the dram physical
high part address for DMA operation.
(high part physical address bit[7:0] – 4)

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16 17:44:08 +02:00
..
allwinner-i2c.c hw, target: Add ResetType argument to hold and exit phase methods 2024-04-25 10:21:06 +01:00
arm_sbcon_i2c.c hw/i2c/versatile_i2c: Rename versatile_i2c -> arm_sbcon_i2c 2023-01-23 13:32:38 +00:00
aspeed_i2c.c hw/i2c/aspeed: Add support for 64 bit addresses 2024-09-16 17:44:08 +02:00
bcm2835_i2c.c hw: Use device_class_set_legacy_reset() instead of opencoding 2024-09-13 15:31:44 +01:00
bitbang_i2c.c hw/i2c: Fix bitbang_i2c_data trace event 2023-08-07 13:52:59 +03:00
core.c hw/i2c: Constify VMState 2023-12-29 11:17:30 +11:00
exynos4210_i2c.c hw: Use device_class_set_legacy_reset() instead of opencoding 2024-09-13 15:31:44 +01:00
i2c_mux_pca954x.c hw/i2c: Enable an id for the pca954x devices 2023-06-13 11:28:58 +02:00
imx_i2c.c hw: Use device_class_set_legacy_reset() instead of opencoding 2024-09-13 15:31:44 +01:00
Kconfig hw/i2c: Implement Broadcom Serial Controller (BSC) 2024-03-05 13:22:55 +00:00
meson.build hw/i2c: Implement Broadcom Serial Controller (BSC) 2024-03-05 13:22:55 +00:00
microbit_i2c.c hw: Use device_class_set_legacy_reset() instead of opencoding 2024-09-13 15:31:44 +01:00
mpc_i2c.c hw: Use device_class_set_legacy_reset() instead of opencoding 2024-09-13 15:31:44 +01:00
npcm7xx_smbus.c hw, target: Add ResetType argument to hold and exit phase methods 2024-04-25 10:21:06 +01:00
omap_i2c.c hw: Use device_class_set_legacy_reset() instead of opencoding 2024-09-13 15:31:44 +01:00
pm_smbus.c hw/i2c: Constify VMState 2023-12-29 11:17:30 +11:00
pmbus_device.c hw/i2c: Constify VMState 2023-12-29 11:17:30 +11:00
ppc4xx_i2c.c hw: Use device_class_set_legacy_reset() instead of opencoding 2024-09-13 15:31:44 +01:00
smbus_eeprom.c hw: Use device_class_set_legacy_reset() instead of opencoding 2024-09-13 15:31:44 +01:00
smbus_ich9.c hw/i2c: Constify VMState 2023-12-29 11:17:30 +11:00
smbus_master.c hw/i2c: Introduce i2c_start_recv() and i2c_start_send() 2021-07-08 14:15:01 -05:00
smbus_slave.c hw/i2c/smbus_slave: Add object path on error prints 2024-02-22 12:47:40 +01:00
trace-events hw/i2c/pm_smbus: Convert DPRINTF to trace events 2023-11-02 13:36:45 +00:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00