hw/i2c/versatile_i2c: Rename versatile_i2c -> arm_sbcon_i2c
This device model started with the Versatile board, named TYPE_VERSATILE_I2C, then ended up renamed TYPE_ARM_SBCON_I2C as per the official "ARM SBCon two-wire serial bus interface" description from: https://developer.arm.com/documentation/dui0440/b/programmer-s-reference/two-wire-serial-bus-interface--sbcon Use the latter name as a better description. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230110082508.24038-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -942,6 +942,7 @@ M: Peter Maydell <peter.maydell@linaro.org>
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L: qemu-arm@nongnu.org
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S: Maintained
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F: hw/*/versatile*
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F: hw/i2c/arm_sbcon_i2c.c
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F: include/hw/i2c/arm_sbcon_i2c.h
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F: hw/misc/arm_sysctl.c
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F: docs/system/arm/versatile.rst
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@ -211,7 +211,7 @@ config REALVIEW
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select PL110
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select PL181 # display
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select PL310 # cache controller
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select VERSATILE_I2C
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select ARM_SBCON_I2C
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select DS1338 # I2C RTC+NVRAM
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select USB_OHCI
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@ -481,7 +481,7 @@ config MPS2
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select SPLIT_IRQ
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select UNIMP
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select CMSDK_APB_WATCHDOG
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select VERSATILE_I2C
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select ARM_SBCON_I2C
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config FSL_IMX7
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bool
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@ -14,7 +14,7 @@ config SMBUS_EEPROM
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bool
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select SMBUS
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config VERSATILE_I2C
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config ARM_SBCON_I2C
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bool
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select BITBANG_I2C
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@ -37,7 +37,7 @@ REG32(CONTROL_CLR, 4)
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#define SCL BIT(0)
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#define SDA BIT(1)
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static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
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static uint64_t arm_sbcon_i2c_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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ArmSbconI2CState *s = opaque;
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@ -52,7 +52,7 @@ static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
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}
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}
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static void versatile_i2c_write(void *opaque, hwaddr offset,
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static void arm_sbcon_i2c_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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ArmSbconI2CState *s = opaque;
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@ -72,13 +72,13 @@ static void versatile_i2c_write(void *opaque, hwaddr offset,
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s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
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}
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static const MemoryRegionOps versatile_i2c_ops = {
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.read = versatile_i2c_read,
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.write = versatile_i2c_write,
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static const MemoryRegionOps arm_sbcon_i2c_ops = {
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.read = arm_sbcon_i2c_read,
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.write = arm_sbcon_i2c_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void versatile_i2c_init(Object *obj)
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static void arm_sbcon_i2c_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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ArmSbconI2CState *s = ARM_SBCON_I2C(obj);
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@ -87,21 +87,21 @@ static void versatile_i2c_init(Object *obj)
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bus = i2c_init_bus(dev, "i2c");
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bitbang_i2c_init(&s->bitbang, bus);
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memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
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memory_region_init_io(&s->iomem, obj, &arm_sbcon_i2c_ops, s,
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"arm_sbcon_i2c", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const TypeInfo versatile_i2c_info = {
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static const TypeInfo arm_sbcon_i2c_info = {
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.name = TYPE_ARM_SBCON_I2C,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ArmSbconI2CState),
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.instance_init = versatile_i2c_init,
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.instance_init = arm_sbcon_i2c_init,
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};
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static void versatile_i2c_register_types(void)
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static void arm_sbcon_i2c_register_types(void)
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{
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type_register_static(&versatile_i2c_info);
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type_register_static(&arm_sbcon_i2c_info);
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}
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type_init(versatile_i2c_register_types)
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type_init(arm_sbcon_i2c_register_types)
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@ -12,7 +12,7 @@ i2c_ss.add(when: 'CONFIG_ALLWINNER_I2C', if_true: files('allwinner-i2c.c'))
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i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c'))
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i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c'))
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i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c'))
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i2c_ss.add(when: 'CONFIG_VERSATILE_I2C', if_true: files('versatile_i2c.c'))
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i2c_ss.add(when: 'CONFIG_ARM_SBCON_I2C', if_true: files('arm_sbcon_i2c.c'))
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i2c_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_i2c.c'))
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i2c_ss.add(when: 'CONFIG_PPC4XX', if_true: files('ppc4xx_i2c.c'))
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i2c_ss.add(when: 'CONFIG_PCA954X', if_true: files('i2c_mux_pca954x.c'))
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