qemu/include/hw/riscv
Bin Meng 59f74489cf hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
Commit 28d8c28120 ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine")
changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES
should include interrupt source 0 but "riscv,ndev" does not.

While we are here, we also fix the comments of platform bus irq range
which is now "64 to 96", but should be "64 to 95", introduced since
commit 1832b7cb3f ("hw/riscv: virt: Create a platform bus").

Fixes: 28d8c28120 ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-13-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06 10:42:55 +10:00
..
boot_opensbi.h Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
boot.h hw/riscv: virt: Enable booting S-mode firmware from pflash 2022-10-14 14:29:50 +10:00
microchip_pfsoc.h hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC 2023-01-06 10:42:55 +10:00
numa.h hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.h hw/riscv/opentitan: add aon_timer base unimpl 2023-01-06 10:42:55 +10:00
riscv_hart.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
shakti_c.h Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
sifive_cpu.h riscv: Add a sifive_cpu.h to include both E and U cpu type defines 2019-09-17 08:42:46 -07:00
sifive_e.h hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC 2023-01-06 10:42:55 +10:00
sifive_u.h hw/riscv: sifive_u: Use the PLIC config helper function 2021-10-28 14:39:23 +10:00
spike.h hw/riscv: spike: Allow using binary firmware as bios 2022-01-21 15:52:56 +10:00
virt.h hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb 2023-01-06 10:42:55 +10:00