aefd1108ee
Adds the updated `aon_timer` base as an unimplemented device. This is used by TockOS, patch ensures the guest doesn't hit load faults. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221025043335.339815-3-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
119 lines
2.9 KiB
C
119 lines
2.9 KiB
C
/*
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* QEMU RISC-V Board Compatible with OpenTitan FPGA platform
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*
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* Copyright (c) 2020 Western Digital
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_OPENTITAN_H
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#define HW_OPENTITAN_H
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#include "hw/riscv/riscv_hart.h"
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#include "hw/intc/sifive_plic.h"
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#include "hw/char/ibex_uart.h"
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#include "hw/timer/ibex_timer.h"
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#include "hw/ssi/ibex_spi_host.h"
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#include "qom/object.h"
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#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
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OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
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enum {
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OPENTITAN_SPI_HOST0,
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OPENTITAN_SPI_HOST1,
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OPENTITAN_NUM_SPI_HOSTS,
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};
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struct LowRISCIbexSoCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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RISCVHartArrayState cpus;
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SiFivePLICState plic;
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IbexUartState uart;
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IbexTimerState timer;
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IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
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uint32_t resetvec;
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MemoryRegion flash_mem;
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MemoryRegion rom;
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MemoryRegion flash_alias;
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};
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typedef struct OpenTitanState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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LowRISCIbexSoCState soc;
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} OpenTitanState;
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enum {
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IBEX_DEV_ROM,
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IBEX_DEV_RAM,
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IBEX_DEV_FLASH,
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IBEX_DEV_FLASH_VIRTUAL,
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IBEX_DEV_UART,
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IBEX_DEV_SPI_DEVICE,
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IBEX_DEV_SPI_HOST0,
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IBEX_DEV_SPI_HOST1,
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IBEX_DEV_GPIO,
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IBEX_DEV_I2C,
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IBEX_DEV_PATTGEN,
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IBEX_DEV_TIMER,
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IBEX_DEV_SENSOR_CTRL,
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IBEX_DEV_OTP_CTRL,
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IBEX_DEV_LC_CTRL,
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IBEX_DEV_PWRMGR,
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IBEX_DEV_RSTMGR,
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IBEX_DEV_CLKMGR,
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IBEX_DEV_PINMUX,
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IBEX_DEV_AON_TIMER,
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IBEX_DEV_USBDEV,
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IBEX_DEV_FLASH_CTRL,
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IBEX_DEV_PLIC,
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IBEX_DEV_AES,
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IBEX_DEV_HMAC,
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IBEX_DEV_KMAC,
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IBEX_DEV_KEYMGR,
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IBEX_DEV_CSRNG,
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IBEX_DEV_ENTROPY,
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IBEX_DEV_EDNO,
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IBEX_DEV_EDN1,
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IBEX_DEV_ALERT_HANDLER,
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IBEX_DEV_NMI_GEN,
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IBEX_DEV_OTBN,
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IBEX_DEV_PERI,
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};
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enum {
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IBEX_UART0_TX_WATERMARK_IRQ = 1,
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IBEX_UART0_RX_WATERMARK_IRQ = 2,
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IBEX_UART0_TX_EMPTY_IRQ = 3,
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IBEX_UART0_RX_OVERFLOW_IRQ = 4,
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IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
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IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
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IBEX_UART0_RX_TIMEOUT_IRQ = 7,
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IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
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IBEX_TIMER_TIMEREXPIRED0_0 = 127,
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IBEX_SPI_HOST0_ERR_IRQ = 134,
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IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135,
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IBEX_SPI_HOST1_ERR_IRQ = 136,
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IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137,
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};
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#endif
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