qemu/target/riscv
Weiwei Li 4556fdaa5c target/riscv: Add properties for BF16 extensions
Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
Add require check for BF16 extensions.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230615063302.102409-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10 22:29:15 +10:00
..
insn_trans target/riscv: Enable PC-relative translation 2023-06-13 17:37:12 +10:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu_bits.h riscv: Make sure an exception is raised if a pte is malformed 2023-05-05 10:49:50 +10:00
cpu_cfg.h target/riscv: Add properties for BF16 extensions 2023-07-10 22:29:15 +10:00
cpu_helper.c target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV 2023-07-10 22:29:14 +10:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu-param.h target/riscv: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu-qom.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu.c target/riscv: Add properties for BF16 extensions 2023-07-10 22:29:15 +10:00
cpu.h target/riscv: Add additional xlen for address when MPRV=1 2023-07-10 22:29:14 +10:00
crypto_helper.c target/riscv: Use aesdec_ISB_ISR_IMC_AK 2023-07-09 13:47:17 +01:00
csr.c target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV 2023-07-10 22:29:14 +10:00
debug.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
debug.h target/riscv: Add itrigger support when icount is enabled 2023-01-06 10:42:55 +10:00
fpu_helper.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
gdbstub.c target/riscv: Use PRV_RESERVED instead of PRV_H 2023-05-05 10:49:50 +10:00
helper.h target/riscv: Handle HLV, HSV via helpers 2023-05-05 10:49:50 +10:00
insn16.decode target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn32.decode target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder 2023-03-05 11:49:43 -08:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: Introduce mmuidx_2stage 2023-05-05 10:49:50 +10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm_riscv.h target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm-stub.c target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm.c target/riscv: fix SBI getchar handler for KVM 2023-02-07 08:19:23 +10:00
m128_helper.c target/riscv: Fix format for indentation 2023-05-05 10:49:50 +10:00
machine.c target/riscv: Restrict KVM-specific fields from ArchCPU 2023-06-28 14:27:59 +02:00
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
monitor.c target/riscv: remove RISCV_FEATURE_MMU 2023-03-01 13:47:15 -08:00
op_helper.c target/riscv: Make MPV only work when MPP != PRV_M 2023-07-10 22:29:14 +10:00
pmp.c target/riscv: Smepmp: Return error when access permission not allowed in PMP 2023-06-13 17:45:30 +10:00
pmp.h target/riscv: Change the return type of pmp_hart_has_privs() to bool 2023-06-13 17:09:13 +10:00
pmu.c target/riscv: Fix lines with over 80 characters 2023-05-05 10:49:50 +10:00
pmu.h riscv: Clean up includes 2023-02-08 07:28:05 +01:00
riscv-qmp-cmds.c target/riscv: add TYPE_RISCV_DYNAMIC_CPU 2023-05-05 10:49:50 +10:00
sbi_ecall_interface.h target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
time_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: Add additional xlen for address when MPRV=1 2023-07-10 22:29:14 +10:00
vector_helper.c target/riscv/vector_helper.c: Remove the check for extra tail elements 2023-06-13 17:44:41 +10:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00