.. |
insn_trans
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target/riscv: Enable PC-relative translation
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2023-06-13 17:37:12 +10:00 |
arch_dump.c
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target/riscv: Fix format for comments
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2023-05-05 10:49:50 +10:00 |
bitmanip_helper.c
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target/riscv: rvk: add support for zbkx extension
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2022-04-29 10:47:45 +10:00 |
common-semi-target.h
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semihosting: Split out common-semi-target.h
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2022-06-28 04:35:07 +05:30 |
cpu_bits.h
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riscv: Make sure an exception is raised if a pte is malformed
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2023-05-05 10:49:50 +10:00 |
cpu_cfg.h
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target/riscv: Add properties for BF16 extensions
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2023-07-10 22:29:15 +10:00 |
cpu_helper.c
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target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV
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2023-07-10 22:29:14 +10:00 |
cpu_user.h
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Supply missing header guards
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2019-06-12 13:20:21 +02:00 |
cpu_vendorid.h
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target/riscv: add Ventana's Veyron V1 CPU
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2023-05-05 10:49:50 +10:00 |
cpu-param.h
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target/riscv: Remove NB_MMU_MODES define
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2023-03-13 06:44:37 -07:00 |
cpu-qom.h
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target/riscv: add Ventana's Veyron V1 CPU
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2023-05-05 10:49:50 +10:00 |
cpu.c
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target/riscv: Add properties for BF16 extensions
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2023-07-10 22:29:15 +10:00 |
cpu.h
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target/riscv: Add additional xlen for address when MPRV=1
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2023-07-10 22:29:14 +10:00 |
crypto_helper.c
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target/riscv: Use aesdec_ISB_ISR_IMC_AK
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2023-07-09 13:47:17 +01:00 |
csr.c
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target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV
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2023-07-10 22:29:14 +10:00 |
debug.c
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target/riscv: Fix lines with over 80 characters
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2023-05-05 10:49:50 +10:00 |
debug.h
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target/riscv: Add itrigger support when icount is enabled
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2023-01-06 10:42:55 +10:00 |
fpu_helper.c
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target/riscv: Fix format for indentation
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2023-05-05 10:49:50 +10:00 |
gdbstub.c
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target/riscv: Use PRV_RESERVED instead of PRV_H
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2023-05-05 10:49:50 +10:00 |
helper.h
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target/riscv: Handle HLV, HSV via helpers
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2023-05-05 10:49:50 +10:00 |
insn16.decode
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target/riscv: add support for Zcmt extension
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2023-05-05 10:49:50 +10:00 |
insn32.decode
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target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder
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2023-03-05 11:49:43 -08:00 |
instmap.h
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target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
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2022-09-07 09:18:32 +02:00 |
internals.h
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target/riscv: Introduce mmuidx_2stage
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2023-05-05 10:49:50 +10:00 |
Kconfig
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meson: Introduce target-specific Kconfig
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2021-07-09 18:21:34 +02:00 |
kvm_riscv.h
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target/riscv: Support setting external interrupt by KVM
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2022-01-21 15:52:56 +10:00 |
kvm-stub.c
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target/riscv: Support setting external interrupt by KVM
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2022-01-21 15:52:56 +10:00 |
kvm.c
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target/riscv: fix SBI getchar handler for KVM
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2023-02-07 08:19:23 +10:00 |
m128_helper.c
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target/riscv: Fix format for indentation
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2023-05-05 10:49:50 +10:00 |
machine.c
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target/riscv: Restrict KVM-specific fields from ArchCPU
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2023-06-28 14:27:59 +02:00 |
meson.build
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meson: Replace softmmu_ss -> system_ss
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2023-06-20 10:01:30 +02:00 |
monitor.c
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target/riscv: remove RISCV_FEATURE_MMU
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2023-03-01 13:47:15 -08:00 |
op_helper.c
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target/riscv: Make MPV only work when MPP != PRV_M
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2023-07-10 22:29:14 +10:00 |
pmp.c
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target/riscv: Smepmp: Return error when access permission not allowed in PMP
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2023-06-13 17:45:30 +10:00 |
pmp.h
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target/riscv: Change the return type of pmp_hart_has_privs() to bool
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2023-06-13 17:09:13 +10:00 |
pmu.c
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target/riscv: Fix lines with over 80 characters
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2023-05-05 10:49:50 +10:00 |
pmu.h
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riscv: Clean up includes
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2023-02-08 07:28:05 +01:00 |
riscv-qmp-cmds.c
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target/riscv: add TYPE_RISCV_DYNAMIC_CPU
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2023-05-05 10:49:50 +10:00 |
sbi_ecall_interface.h
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target/riscv: Fix format for comments
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2023-05-05 10:49:50 +10:00 |
time_helper.c
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target/riscv: Simplify type conversion for CPURISCVState
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2023-05-05 10:49:49 +10:00 |
time_helper.h
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target/riscv: Simplify type conversion for CPURISCVState
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2023-05-05 10:49:49 +10:00 |
trace-events
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target/riscv: Add ePMP CSR access functions
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2021-05-11 20:02:06 +10:00 |
trace.h
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trace: switch position of headers to what Meson requires
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2020-08-21 06:18:24 -04:00 |
translate.c
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target/riscv: Add additional xlen for address when MPRV=1
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2023-07-10 22:29:14 +10:00 |
vector_helper.c
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target/riscv/vector_helper.c: Remove the check for extra tail elements
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2023-06-13 17:44:41 +10:00 |
xthead.decode
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RISC-V: Adding XTheadFmv ISA extension
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2023-02-07 08:19:23 +10:00 |
XVentanaCondOps.decode
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target/riscv: Add XVentanaCondOps custom extension
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2022-02-16 12:24:18 +10:00 |
zce_helper.c
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target/riscv: add support for Zcmt extension
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2023-05-05 10:49:50 +10:00 |