Siarhei Volkau 3f0e94c134 target/mips/mxu: Add S8STD S8LDI S8SDI instructions ... These instructions are all load/store a byte from memory and put it into/get it from MXU register in various combinations. I-suffix instructions modify the base address GPR by offset provided. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-21-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2023-07-10 23:33:38 +02:00
..
sysemu	target/mips: Rework cp0_timer with clock API	2023-07-10 21:53:03 +02:00
tcg	target/mips/mxu: Add S8STD S8LDI S8SDI instructions	2023-07-10 23:33:38 +02:00
cpu-defs.c.inc	target/mips: Add support of two XBurst CPUs	2023-07-10 23:33:38 +02:00
cpu-param.h	target/mips: Remove NB_MMU_MODES define	2023-03-13 06:44:37 -07:00
cpu-qom.h	target/mips: Convert to 3-phase reset	2022-12-16 15:58:15 +00:00
cpu.c	target/mips: Implement Loongson CSR instructions	2023-07-10 23:33:37 +02:00
cpu.h	target/mips: Implement Loongson CSR instructions	2023-07-10 23:33:37 +02:00
fpu_helper.h
fpu.c
gdbstub.c	gdbstub: move register helpers into standalone include	2023-03-07 20:44:08 +00:00
helper.h	target/mips: Implement Loongson CSR instructions	2023-07-10 23:33:37 +02:00
internal.h	target/mips: Implement Loongson CSR instructions	2023-07-10 23:33:37 +02:00
Kconfig
kvm_mips.h
kvm.c	mips: Remove support for trap and emulate KVM	2023-01-13 09:32:32 +01:00
meson.build	meson: Replace softmmu_ss -> system_ss	2023-06-20 10:01:30 +02:00
mips-defs.h	target/mips: introduce decodetree structure for Cavium Octeon extension	2022-07-12 22:30:09 +02:00
msa.c