target/mips: Convert to 3-phase reset
Convert the mips CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-id: 20221124115023.2437291-11-peter.maydell@linaro.org
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@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
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/**
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* MIPSCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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* @parent_phases: The parent class' reset phase handlers.
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*
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* A MIPS CPU model.
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*/
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@ -44,7 +44,7 @@ struct MIPSCPUClass {
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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ResettablePhases parent_phases;
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const struct mips_def_t *cpu_def;
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/* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
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@ -182,14 +182,16 @@ static bool mips_cpu_has_work(CPUState *cs)
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#include "cpu-defs.c.inc"
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static void mips_cpu_reset(DeviceState *dev)
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static void mips_cpu_reset_hold(Object *obj)
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{
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CPUState *cs = CPU(dev);
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CPUState *cs = CPU(obj);
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MIPSCPU *cpu = MIPS_CPU(cs);
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MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
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CPUMIPSState *env = &cpu->env;
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mcc->parent_reset(dev);
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if (mcc->parent_phases.hold) {
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mcc->parent_phases.hold(obj);
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}
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memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
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@ -562,10 +564,12 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
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MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
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CPUClass *cc = CPU_CLASS(c);
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DeviceClass *dc = DEVICE_CLASS(c);
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ResettableClass *rc = RESETTABLE_CLASS(c);
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device_class_set_parent_realize(dc, mips_cpu_realizefn,
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&mcc->parent_realize);
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device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
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resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL,
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&mcc->parent_phases);
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cc->class_by_name = mips_cpu_class_by_name;
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cc->has_work = mips_cpu_has_work;
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