qemu/target/avr
Richard Henderson 119065574d hw/core: Constify TCGCPUOps
We no longer have any runtime modifications to this struct,
so declare them all const.

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org>
2021-05-26 15:33:59 -07:00
..
cpu-param.h target/avr: Add basic parameters of the new platform 2020-07-10 17:58:32 +02:00
cpu-qom.h qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros 2020-09-18 14:12:32 -04:00
cpu.c hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
cpu.h target/avr: Add support for disassembling via option '-d in_asm' 2020-07-11 11:02:05 +02:00
disas.c meson: target 2020-08-21 06:30:35 -04:00
gdbstub.c target/avr: CPU class: Add GDB support 2020-07-10 17:58:32 +02:00
helper.c target/avr: Ignore unimplemented WDR opcode 2021-05-13 19:18:42 +02:00
helper.h target/avr: Add instruction helpers 2020-07-11 11:02:05 +02:00
insn.decode target/avr: Add instruction translation - MCU Control Instructions 2020-07-11 11:02:05 +02:00
machine.c cpu: Move AVR target vmsd field from CPUClass to DeviceClass 2021-05-26 15:33:59 -07:00
meson.build meson: target 2020-08-21 06:30:35 -04:00
translate.c meson: target 2020-08-21 06:30:35 -04:00