target/avr: Add support for disassembling via option '-d in_asm'
Provide function disassembles executed instruction when '-d in_asm' is
provided.
Example:
$ qemu-system-avr -bios free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf -d in_asm
...
IN:
0x0000014a: CALL 0x3808
IN: main
0x00003808: CALL 0x4b4
IN: vParTestInitialise
0x000004b4: LDI r24, 255
0x000004b6: STS r24, 0
0x000004b8: MULS r16, r20
0x000004ba: OUT $1, r24
0x000004bc: LDS r24, 0
0x000004be: MULS r16, r20
0x000004c0: OUT $2, r24
0x000004c2: RET
...
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
[rth: Fix spacing and const mnemonic arrays]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-19-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Rolnik
Philippe Mathieu-Daudé
parent
a107fdb072
commit
9d8caa67a2
@ -85,7 +85,7 @@ static void avr_cpu_reset(DeviceState *ds)
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static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_arch_avr;
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info->print_insn = NULL;
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info->print_insn = avr_print_insn;
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}
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static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
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@ -161,6 +161,7 @@ bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
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hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int avr_print_insn(bfd_vma addr, disassemble_info *info);
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static inline int avr_feature(CPUAVRState *env, AVRFeature feature)
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{
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245
target/avr/disas.c
Normal file
245
target/avr/disas.c
Normal file
@ -0,0 +1,245 @@
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/*
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* AVR disassembler
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*
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* Copyright (c) 2019-2020 Richard Henderson <rth@twiddle.net>
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* Copyright (c) 2019-2020 Michael Rolnik <mrolnik@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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typedef struct {
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disassemble_info *info;
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uint16_t next_word;
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bool next_word_used;
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} DisasContext;
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static int to_regs_16_31_by_one(DisasContext *ctx, int indx)
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{
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return 16 + (indx % 16);
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}
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static int to_regs_16_23_by_one(DisasContext *ctx, int indx)
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{
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return 16 + (indx % 8);
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}
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static int to_regs_24_30_by_two(DisasContext *ctx, int indx)
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{
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return 24 + (indx % 4) * 2;
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}
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static int to_regs_00_30_by_two(DisasContext *ctx, int indx)
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{
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return (indx % 16) * 2;
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}
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static uint16_t next_word(DisasContext *ctx)
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{
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ctx->next_word_used = true;
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return ctx->next_word;
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}
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static int append_16(DisasContext *ctx, int x)
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{
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return x << 16 | next_word(ctx);
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}
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/* Include the auto-generated decoder. */
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static bool decode_insn(DisasContext *ctx, uint16_t insn);
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#include "decode_insn.inc.c"
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#define output(mnemonic, format, ...) \
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(pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \
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mnemonic, ##__VA_ARGS__))
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int avr_print_insn(bfd_vma addr, disassemble_info *info)
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{
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DisasContext ctx;
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DisasContext *pctx = &ctx;
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bfd_byte buffer[4];
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uint16_t insn;
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int status;
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ctx.info = info;
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status = info->read_memory_func(addr, buffer, 4, info);
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if (status != 0) {
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info->memory_error_func(status, addr, info);
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return -1;
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}
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insn = bfd_getl16(buffer);
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ctx.next_word = bfd_getl16(buffer + 2);
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ctx.next_word_used = false;
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if (!decode_insn(&ctx, insn)) {
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output(".db", "0x%02x, 0x%02x", buffer[0], buffer[1]);
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}
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return ctx.next_word_used ? 4 : 2;
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}
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#define INSN(opcode, format, ...) \
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static bool trans_##opcode(DisasContext *pctx, arg_##opcode * a) \
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{ \
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output(#opcode, format, ##__VA_ARGS__); \
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return true; \
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}
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#define INSN_MNEMONIC(opcode, mnemonic, format, ...) \
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static bool trans_##opcode(DisasContext *pctx, arg_##opcode * a) \
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{ \
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output(mnemonic, format, ##__VA_ARGS__); \
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return true; \
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}
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/*
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* C Z N V S H T I
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* 0 1 2 3 4 5 6 7
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*/
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static const char brbc[][5] = {
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"BRCC", "BRNE", "BRPL", "BRVC", "BRGE", "BRHC", "BRTC", "BRID"
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};
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static const char brbs[][5] = {
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"BRCS", "BREQ", "BRMI", "BRVS", "BRLT", "BRHS", "BRTS", "BRIE"
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};
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static const char bset[][4] = {
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"SEC", "SEZ", "SEN", "SEZ", "SES", "SEH", "SET", "SEI"
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};
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static const char bclr[][4] = {
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"CLC", "CLZ", "CLN", "CLZ", "CLS", "CLH", "CLT", "CLI"
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};
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/*
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* Arithmetic Instructions
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*/
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INSN(ADD, "r%d, r%d", a->rd, a->rr)
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INSN(ADC, "r%d, r%d", a->rd, a->rr)
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INSN(ADIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
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INSN(SUB, "r%d, r%d", a->rd, a->rr)
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INSN(SUBI, "r%d, %d", a->rd, a->imm)
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INSN(SBC, "r%d, r%d", a->rd, a->rr)
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INSN(SBCI, "r%d, %d", a->rd, a->imm)
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INSN(SBIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
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INSN(AND, "r%d, r%d", a->rd, a->rr)
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INSN(ANDI, "r%d, %d", a->rd, a->imm)
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INSN(OR, "r%d, r%d", a->rd, a->rr)
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INSN(ORI, "r%d, %d", a->rd, a->imm)
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INSN(EOR, "r%d, r%d", a->rd, a->rr)
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INSN(COM, "r%d", a->rd)
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INSN(NEG, "r%d", a->rd)
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INSN(INC, "r%d", a->rd)
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INSN(DEC, "r%d", a->rd)
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INSN(MUL, "r%d, r%d", a->rd, a->rr)
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INSN(MULS, "r%d, r%d", a->rd, a->rr)
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INSN(MULSU, "r%d, r%d", a->rd, a->rr)
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INSN(FMUL, "r%d, r%d", a->rd, a->rr)
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INSN(FMULS, "r%d, r%d", a->rd, a->rr)
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INSN(FMULSU, "r%d, r%d", a->rd, a->rr)
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INSN(DES, "%d", a->imm)
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/*
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* Branch Instructions
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*/
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INSN(RJMP, ".%+d", a->imm * 2)
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INSN(IJMP, "")
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INSN(EIJMP, "")
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INSN(JMP, "0x%x", a->imm * 2)
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INSN(RCALL, ".%+d", a->imm * 2)
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INSN(ICALL, "")
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INSN(EICALL, "")
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INSN(CALL, "0x%x", a->imm * 2)
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INSN(RET, "")
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INSN(RETI, "")
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INSN(CPSE, "r%d, r%d", a->rd, a->rr)
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INSN(CP, "r%d, r%d", a->rd, a->rr)
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INSN(CPC, "r%d, r%d", a->rd, a->rr)
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INSN(CPI, "r%d, %d", a->rd, a->imm)
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INSN(SBRC, "r%d, %d", a->rr, a->bit)
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INSN(SBRS, "r%d, %d", a->rr, a->bit)
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INSN(SBIC, "$%d, %d", a->reg, a->bit)
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INSN(SBIS, "$%d, %d", a->reg, a->bit)
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INSN_MNEMONIC(BRBS, brbs[a->bit], ".%+d", a->imm * 2)
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INSN_MNEMONIC(BRBC, brbc[a->bit], ".%+d", a->imm * 2)
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/*
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* Data Transfer Instructions
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*/
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INSN(MOV, "r%d, r%d", a->rd, a->rr)
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INSN(MOVW, "r%d:r%d, r%d:r%d", a->rd + 1, a->rd, a->rr + 1, a->rr)
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INSN(LDI, "r%d, %d", a->rd, a->imm)
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INSN(LDS, "r%d, %d", a->rd, a->imm)
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INSN(LDX1, "r%d, X", a->rd)
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INSN(LDX2, "r%d, X+", a->rd)
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INSN(LDX3, "r%d, -X", a->rd)
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INSN(LDY2, "r%d, Y+", a->rd)
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INSN(LDY3, "r%d, -Y", a->rd)
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INSN(LDZ2, "r%d, Z+", a->rd)
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INSN(LDZ3, "r%d, -Z", a->rd)
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INSN(LDDY, "r%d, Y+%d", a->rd, a->imm)
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INSN(LDDZ, "r%d, Z+%d", a->rd, a->imm)
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INSN(STS, "r%d, %d", a->rd, a->imm)
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INSN(STX1, "r%d, X", a->rr)
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INSN(STX2, "r%d, X+", a->rr)
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INSN(STX3, "r%d, -X", a->rr)
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INSN(STY2, "r%d, Y+", a->rd)
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INSN(STY3, "r%d, -Y", a->rd)
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INSN(STZ2, "r%d, Z+", a->rd)
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INSN(STZ3, "r%d, -Z", a->rd)
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INSN(STDY, "r%d, Y+%d", a->rd, a->imm)
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INSN(STDZ, "r%d, Z+%d", a->rd, a->imm)
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INSN(LPM1, "")
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INSN(LPM2, "r%d, Z", a->rd)
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INSN(LPMX, "r%d, Z+", a->rd)
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INSN(ELPM1, "")
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INSN(ELPM2, "r%d, Z", a->rd)
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INSN(ELPMX, "r%d, Z+", a->rd)
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INSN(SPM, "")
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INSN(SPMX, "Z+")
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INSN(IN, "r%d, $%d", a->rd, a->imm)
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INSN(OUT, "$%d, r%d", a->imm, a->rd)
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INSN(PUSH, "r%d", a->rd)
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INSN(POP, "r%d", a->rd)
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INSN(XCH, "Z, r%d", a->rd)
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INSN(LAC, "Z, r%d", a->rd)
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INSN(LAS, "Z, r%d", a->rd)
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INSN(LAT, "Z, r%d", a->rd)
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/*
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* Bit and Bit-test Instructions
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*/
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INSN(LSR, "r%d", a->rd)
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INSN(ROR, "r%d", a->rd)
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INSN(ASR, "r%d", a->rd)
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INSN(SWAP, "r%d", a->rd)
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INSN(SBI, "$%d, %d", a->reg, a->bit)
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INSN(CBI, "%d, %d", a->reg, a->bit)
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INSN(BST, "r%d, %d", a->rd, a->bit)
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INSN(BLD, "r%d, %d", a->rd, a->bit)
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INSN_MNEMONIC(BSET, bset[a->bit], "")
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INSN_MNEMONIC(BCLR, bclr[a->bit], "")
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/*
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* MCU Control Instructions
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*/
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INSN(BREAK, "")
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INSN(NOP, "")
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INSN(SLEEP, "")
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INSN(WDR, "")
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@ -3040,6 +3040,18 @@ done_generating:
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tb->size = (ctx.npc - pc_start) * 2;
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tb->icount = num_insns;
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#ifdef DEBUG_DISAS
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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&& qemu_log_in_addr_range(tb->pc)) {
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FILE *fd;
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fd = qemu_log_lock();
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qemu_log("IN: %s\n", lookup_symbol(tb->pc));
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log_target_disas(cs, tb->pc, tb->size);
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qemu_log("\n");
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qemu_log_unlock(fd);
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}
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#endif
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}
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void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb,
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