Christoph Muellner 260b594d8a RISC-V: Add Zawrs ISA extension support ... This patch adds support for the Zawrs ISA extension. Given the current (incomplete) implementation of reservation sets there seems to be no way to provide a full emulation of the WRS instruction (wake on reservation set invalidation or timeout or interrupt). Therefore, we just exit the TB and return to the main loop. The specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Note, that the Zawrs extension is frozen, but not ratified yet. Changes since v3: * Remove "RFC" since the extension is frozen * Rebase on master and fix integration issues * Fix entry ordering in extension list Changes since v2: * Rebase on master and resolve conflicts * Adjustments according to a specification change * Inline REQUIRE_ZAWRS() since it has only one user Changes since v1: * Adding zawrs to the ISA string that is passed to the kernel Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221005144948.3421504-1-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-01-06 10:42:55 +10:00
..
insn_trans	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
arch_dump.c	dump: Replace opaque DumpState pointer with a typed one	2022-10-06 19:30:43 +04:00
bitmanip_helper.c	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu_bits.h	target/riscv: Add smstateen support	2023-01-06 10:42:55 +10:00
cpu_helper.c	target/riscv: support cache-related PMU events in virtual mode	2023-01-06 10:42:55 +10:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu.c	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
cpu.h	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
crypto_helper.c	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
csr.c	target/riscv: Typo fix in sstc() predicate	2023-01-06 10:42:55 +10:00
debug.c	target/riscv: Add itrigger_enabled field to CPURISCVState	2023-01-06 10:42:55 +10:00
debug.h	target/riscv: Add itrigger support when icount is enabled	2023-01-06 10:42:55 +10:00
fpu_helper.c	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
gdbstub.c	target/riscv: Check the correct exception cause in vector GDB stub	2022-09-27 07:04:38 +10:00
helper.h	target/riscv: Add itrigger support when icount is not enabled	2023-01-06 10:42:55 +10:00
insn16.decode	target/riscv: fix shifts shamt value for rv128c	2022-09-07 09:18:32 +02:00
insn32.decode	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: rvv: Add mask agnostic for vv instructions	2022-09-07 09:18:32 +02:00
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
kvm_riscv.h	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm-stub.c	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm.c	kvm: allow target-specific accelerator properties	2022-10-10 09:23:16 +02:00
m128_helper.c	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
machine.c	target/riscv: Add itrigger_enabled field to CPURISCVState	2023-01-06 10:42:55 +10:00
meson.build	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
monitor.c	target/riscv: Fix incorrect PTE merge in walk_pte	2022-04-29 10:47:46 +10:00
op_helper.c	target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+	2023-01-06 10:42:55 +10:00
pmp.c	target/riscv: Fix PMP propagation for tlb	2023-01-06 10:42:55 +10:00
pmp.h	target/riscv: Fix PMP propagation for tlb	2023-01-06 10:42:55 +10:00
pmu.c	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
pmu.h	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
sbi_ecall_interface.h	Clean up ill-advised or unusual header guards	2022-05-11 16:50:01 +02:00
time_helper.c	target/riscv: Add vstimecmp support	2022-09-07 09:19:15 +02:00
time_helper.h	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
vector_helper.c	cleanup: Tweak and re-run return_directly.cocci	2022-12-14 16:19:35 +01:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00