target/riscv: Add itrigger_enabled field to CPURISCVState
Avoid calling riscv_itrigger_enabled() when calculate the tbflags. As the itrigger enable status can only be changed when write tdata1, migration load or itrigger fire, update env->itrigger_enabled at these places. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221013062946.7530-5-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -331,6 +331,7 @@ struct CPUArchState {
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struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
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QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
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int64_t last_icount;
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bool itrigger_enabled;
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/* machine specific rdtime callback */
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uint64_t (*rdtime_fn)(void *);
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@ -106,8 +106,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
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get_field(env->mstatus_hs, MSTATUS_VS));
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}
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if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
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flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER,
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riscv_itrigger_enabled(env));
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flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
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}
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#endif
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@ -563,6 +563,7 @@ void helper_itrigger_match(CPURISCVState *env)
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}
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itrigger_set_count(env, i, count--);
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if (!count) {
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env->itrigger_enabled = riscv_itrigger_enabled(env);
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do_trigger_action(env, i);
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}
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}
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@ -660,6 +661,8 @@ static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
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/* set the count to timer */
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timer_mod(env->itrigger_timer[index],
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env->last_icount + itrigger_get_count(env, index));
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} else {
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env->itrigger_enabled = riscv_itrigger_enabled(env);
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}
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}
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break;
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@ -21,6 +21,8 @@
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#include "qemu/error-report.h"
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#include "sysemu/kvm.h"
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#include "migration/cpu.h"
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#include "sysemu/cpu-timers.h"
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#include "debug.h"
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static bool pmp_needed(void *opaque)
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{
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@ -229,11 +231,24 @@ static bool debug_needed(void *opaque)
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return riscv_feature(env, RISCV_FEATURE_DEBUG);
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}
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static int debug_post_load(void *opaque, int version_id)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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if (icount_enabled()) {
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env->itrigger_enabled = riscv_itrigger_enabled(env);
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}
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return 0;
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}
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static const VMStateDescription vmstate_debug = {
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.name = "cpu/debug",
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.version_id = 2,
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.minimum_version_id = 2,
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.needed = debug_needed,
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.post_load = debug_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
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VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
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