9cf3bc65af
A few deficiencies in the current device model need to be noted. 1. FIFOs are not used. All sends and receives are done directly. 2. Repeated starts are not emulated. Repeated starts can be triggered in real hardware by sending a new read transfer request in the window time between transfer active set of write transfer request and done bit set of the same. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240224191038.2409945-2-rayhan.faizel@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
81 lines
3.4 KiB
C
81 lines
3.4 KiB
C
/*
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* Broadcom Serial Controller (BSC)
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*
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* Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h"
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#include "hw/i2c/i2c.h"
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#include "qom/object.h"
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#define TYPE_BCM2835_I2C "bcm2835-i2c"
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OBJECT_DECLARE_SIMPLE_TYPE(BCM2835I2CState, BCM2835_I2C)
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#define BCM2835_I2C_C 0x0 /* Control */
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#define BCM2835_I2C_S 0x4 /* Status */
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#define BCM2835_I2C_DLEN 0x8 /* Data Length */
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#define BCM2835_I2C_A 0xc /* Slave Address */
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#define BCM2835_I2C_FIFO 0x10 /* FIFO */
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#define BCM2835_I2C_DIV 0x14 /* Clock Divider */
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#define BCM2835_I2C_DEL 0x18 /* Data Delay */
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#define BCM2835_I2C_CLKT 0x20 /* Clock Stretch Timeout */
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#define BCM2835_I2C_C_I2CEN BIT(15) /* I2C enable */
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#define BCM2835_I2C_C_INTR BIT(10) /* Interrupt on RXR */
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#define BCM2835_I2C_C_INTT BIT(9) /* Interrupt on TXW */
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#define BCM2835_I2C_C_INTD BIT(8) /* Interrupt on DONE */
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#define BCM2835_I2C_C_ST BIT(7) /* Start transfer */
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#define BCM2835_I2C_C_CLEAR (BIT(5) | BIT(4)) /* Clear FIFO */
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#define BCM2835_I2C_C_READ BIT(0) /* I2C read mode */
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#define BCM2835_I2C_S_CLKT BIT(9) /* Clock stretch timeout */
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#define BCM2835_I2C_S_ERR BIT(8) /* Slave error */
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#define BCM2835_I2C_S_RXF BIT(7) /* RX FIFO full */
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#define BCM2835_I2C_S_TXE BIT(6) /* TX FIFO empty */
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#define BCM2835_I2C_S_RXD BIT(5) /* RX bytes available */
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#define BCM2835_I2C_S_TXD BIT(4) /* TX space available */
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#define BCM2835_I2C_S_RXR BIT(3) /* RX FIFO needs reading */
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#define BCM2835_I2C_S_TXW BIT(2) /* TX FIFO needs writing */
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#define BCM2835_I2C_S_DONE BIT(1) /* I2C Transfer complete */
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#define BCM2835_I2C_S_TA BIT(0) /* I2C Transfer active */
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struct BCM2835I2CState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion iomem;
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I2CBus *bus;
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qemu_irq irq;
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uint32_t c;
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uint32_t s;
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uint32_t dlen;
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uint32_t a;
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uint32_t div;
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uint32_t del;
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uint32_t clkt;
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uint32_t last_dlen;
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};
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