Frederic Barrat 7e5157696b ppc/pnv: Fix number of registers in the PCIe controller on POWER9 ... The spec defines 3 registers, even though only index 0 and 2 are valid on POWER9. The same model is used on POWER10. Register 1 is defined there but we currently don't use it in skiboot. So we can keep reporting an error on write. Reported by Coverity (CID 1487176). Fixes: 4f9924c4d4 ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge") Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220401091925.770803-1-fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>		2022-04-04 08:49:06 +02:00
..
designware.h	nomaintainer: Fix Lesser GPL version number	2020-11-15 17:04:40 +01:00
gpex.h	hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows	2021-04-30 11:16:52 +01:00
i440fx.h	hw/pci: remove all references to find_i440fx function	2021-09-04 17:34:05 -04:00
mv64361.h	hw/pci-host: Add emulation of Marvell MV64361 PPC system controller	2021-05-04 11:41:25 +10:00
pam.h	hw/pci-host/pam: Replace magic number by PAM_REGIONS_COUNT definition	2020-12-13 17:07:05 +01:00
pnv_phb3_regs.h
pnv_phb3.h	pnv_phb3.h: change TYPE_PNV_PHB3_ROOT_BUS name	2022-01-12 11:28:27 +01:00
pnv_phb4_regs.h	ppc/pnv: Add support for PHB5 "Address-based trigger" mode	2022-03-02 06:51:39 +01:00
pnv_phb4.h	ppc/pnv: Fix number of registers in the PCIe controller on POWER9	2022-04-04 08:49:06 +02:00
ppce500.h
q35.h	hw/pci-host/pam: Replace magic number by PAM_REGIONS_COUNT definition	2020-12-13 17:07:05 +01:00
remote.h	multi-process: setup a machine object for remote device process	2021-02-10 09:23:28 +00:00
sabre.h
spapr.h	spapr: Adjust firmware path of PCI devices	2021-02-10 10:43:50 +11:00
uninorth.h	uninorth: use qdev gpios for PCI IRQs	2020-10-18 16:21:42 +01:00
xilinx-pcie.h	hw/mips/boston: Fix Lesser GPL version number	2020-11-03 16:51:13 +01:00