Alex Bennée 10113b6903 target-arm: A64: Add last AdvSIMD Integer to FP ops
This adds the remaining [US]CVTF operations to the SIMD
shift-immediate, scalar-shift-immediate, two-reg-misc and
scalar-two-reg-misc groups of opcodes.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1394822294-14837-4-git-send-email-peter.maydell@linaro.org
[PMM: added scalar 2-misc and scalar-shift-imm encodings]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17 16:31:47 +00:00
2014-03-17 16:31:46 +00:00
2014-03-12 16:45:25 +00:00
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2014-03-03 09:46:27 +04:00
2014-03-13 20:15:37 +01:00
2014-03-15 13:54:18 +04:00
2014-03-15 18:22:11 +00:00
2014-03-17 14:34:28 +01:00
2014-03-13 15:33:04 +00:00
2014-03-12 17:26:32 +01:00
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2014-03-17 11:50:19 +00:00
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2014-02-21 21:02:23 +01:00
2014-03-13 14:34:16 +00:00
2014-02-25 14:30:28 +01:00
2014-03-17 13:21:11 +01:00
2013-12-04 15:19:00 +01:00
2014-03-05 03:06:24 +01:00
2014-02-17 11:57:23 -05:00
2014-03-13 20:08:15 -07:00
2014-03-17 15:51:57 +00:00

Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org

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